SAM9G15_14 Datasheet, PDF (613/1215 Pages) ATMEL Corporation – ARM-based Embedded MPU

Figure 34-6. SD Card Bus Connections with One Slot
MCDA0 - MCDA3
MCCK
MCCDA
SD CARD
Note: When several HSMCI (x HSMCI) are embedded in a product, MCCK refers to HSMCIx_CK, MCCDA to
HSMCIx_CDA MCDAy to HSMCIx_DAy.
When the HSMCI is configured to operate with SD memory cards, the width of the data bus can be selected in the
HSMCI_SDCR register. Clearing the SDCBUS bit in this register means that the width is one bit; setting it means that the
width is four bits. In the case of High Speed MultiMedia cards, only the data line 0 is used. The other data lines can be
used as independent PIOs.
34.8
High Speed MultiMedia Card Operations
After a power-on reset, the cards are initialized by a special message-based High Speed MultiMedia Card bus protocol.
Each message is represented by one of the following tokens:
 Command: A command is a token that starts an operation. A command is sent from the host either to a single card
(addressed command) or to all connected cards (broadcast command). A command is transferred serially on the
CMD line.
 Response: A response is a token which is sent from an addressed card or (synchronously) from all connected
cards to the host as an answer to a previously received command. A response is transferred serially on the CMD
line.
 Data: Data can be transferred from the card to the host or vice versa. Data is transferred via the data line.
Card addressing is implemented using a session address assigned during the initialization phase by the bus controller to
all currently connected cards. Their unique CID number identifies individual cards.
The structure of commands, responses and data blocks is described in the High Speed MultiMedia Card System
Specification. See also Table 34-6 on page 614.
High Speed MultiMedia Card bus data transfers are composed of these tokens.
There are different types of operations. Addressed operations always contain a command and a response token. In
addition, some operations have a data token; the others transfer their information directly within the command or
response structure. In this case, no data token is present in an operation. The bits on the DAT and the CMD lines are
transferred synchronous to the clock HSMCI Clock.
Two types of data transfer commands are defined:
 Sequential commands: These commands initiate a continuous data stream. They are terminated only when a stop
command follows on the CMD line. This mode reduces the command overhead to an absolute minimum.
 Block-oriented commands: These commands send a data block succeeded by CRC bits.
Both read and write operations allow either single or multiple block transmission. A multiple block transmission is
terminated when a stop command follows on the CMD line similarly to the sequential read or when a multiple block
transmission has a pre-defined block count (See “Data Transfer Operation” on page 616.).
The HSMCI provides a set of registers to perform the entire range of High Speed MultiMedia Card operations.
34.8.1 Command - Response Operation
After reset, the HSMCI is disabled and becomes valid after setting the MCIEN bit in the HSMCI_CR Control Register.
The PWSEN bit saves power by dividing the HSMCI clock by 2^PWSDIV + 1 when the bus is inactive.
SAM9G15 [DATASHEET]
11152F–ATARM–10-Mar-2014
613