SAM9G15_14 Datasheet, PDF (1047/1215 Pages) ATMEL Corporation – ARM-based Embedded MPU

44.7.9 LCD Controller Disable Register
Name:
LCDC_LCDDIS
Address: 0xF8038024
Access:
Write
Reset:
0x00000000
31
30
29
28
27
26
–
–
–
–
–
–
23
22
21
20
19
18
–
–
–
–
–
–
15
14
13
12
11
10
–
–
–
–
PWMRST
DISPRST
7
6
5
4
3
2
–
–
–
–
PWMDIS
DISPDIS
• CLKDIS: LCD Controller Pixel Clock Disable
0: No effect.
1: Disable the pixel clock.
• SYNCDIS: LCD Controller Horizontal and Vertical Synchronization Disable
0: No effect.
1: Disable the synchronization signals after the end of the frame.
• DISPDIS: LCD Controller DISP Signal Disable
0: No effect.
1: Disable the DISP signal.
• PWMDIS: LCD Controller Pulse Width Modulation Disable
0: No effect.
1: Disable the pulse width modulation signal.
• CLKRST: LCD Controller Clock Reset
0: No effect.
1: Reset the pixel clock generator module. The pixel clock duty cycle may be violated.
• SYNCRST: LCD Controller Horizontal and Vertical Synchronization Reset
0: No effect.
1: Reset the timing engine. Both Horizontal and vertical pulse width are violated.
• DISPRST: LCD Controller DISP Signal Reset
0: No effect.
1: Reset the DISP signal.
• PWMRST: LCD Controller PWM Reset
0: No effect.
1: Reset the PWM module, the duty cycle may be violated.
25
–
17
–
9
SYNCRST
1
SYNCDIS
24
–
16
–
8
CLKRST
0
CLKDIS
SAM9G15 [DATASHEET]
11152F–ATARM–10-Mar-2014
1047