SAMA5D44_14 Datasheet, PDF (484/1776 Pages) ATMEL Corporation – Atmel | SMART ARM-based Embedded MPU

30.9 Connection to External Devices
30.9.1 Data Bus Width
A data bus width of 8 or 16 bits can be selected for each chip select. This option is controlled by the bit DBW in the
SMC Mode Register (HSMC_MODE) for the corresponding chip select.
Figure 30-4 shows how to connect a 512 KB x 8-bit memory on NCS2. Figure 30-4 shows how to connect a 512
KB x 16-bit memory on NCS2.
Figure 30-4. Memory Connection for an 8-bit Data Bus
D[7:0]
D[7:0]
SMC
A[18:2]
A1
A0
NWE
NRD
NCS[2]
A[18:2]
A1
A0
Write Enable
Output Enable
Memory Enable
Figure 30-5. Memory Connection for a 16-bit Data Bus
SMC
D[15:0]
A[19:2]
A1
NBS0
NBS1
NWE
NRD
NCS[2]
D[15:0]
A[18:1]
A[0]
Low Byte Enable
High Byte Enable
Write Enable
Output Enable
Memory Enable
30.9.2 Byte Write or Byte Select Access
Each chip select with a 16-bit data bus can operate with one of two different types of write access: Byte Write or
Byte Select. This is controlled by the BAT bit of the HSMC_MODE register for the corresponding chip select.
30.9.2.1 Byte Write Access
Byte Write Access is used to connect 2 x 8-bit devices as a 16-bit memory, and supports one write signal per byte
of the data bus and a single read signal.
Note that the SMC does not allow boot in Byte Write Access mode.
For 16-bit devices, the SMC provides NWR0 and NWR1 write signals for respectively Byte0 (lower byte) and Byte1
(upper byte) of a 16-bit bus. One single read signal (NRD) is provided.
30.9.2.2 Byte Select Access
Byte Select Access is used to connect one 16-bit device. In this mode, read/write operations can be
enabled/disabled at Byte level. One Byte-select line per byte of the data bus is provided. One NRD and one NWE
signal control read and write.
484
SAMA5D4 Series [DATASHEET]
Atmel-11238A-ATARM-SAMA5D4-Datasheet_30-Sep-14