SAMA5D44_14 Datasheet, PDF (1588/1776 Pages) ATMEL Corporation – Atmel | SMART ARM-based Embedded MPU

50.3 Product Dependencies
50.3.1 Power Management
The AES may be clocked through the Power Management Controller (PMC), so the programmer must first to
configure the PMC to enable the AES clock.
50.3.2 Interrupt
The AES interface has an interrupt line connected to the Interrupt Controller.
Handling the AES interrupt requires programming the Interrupt Controller before configuring the AES.
Table 50-1. Peripheral IDs
Instance
ID
AES
12
50.4
Functional Description
The Advanced Encryption Standard (AES) specifies a FIPS-approved cryptographic algorithm that can be used to
protect electronic data. The AES algorithm is a symmetric block cipher that can encrypt (encipher) and decrypt
(decipher) information.
Encryption converts data to an unintelligible form called ciphertext. Decrypting the ciphertext converts the data
back into its original form, called plaintext. The CIPHER bit in the AES Mode Register (AES_MR) allows selection
between the encryption and the decryption processes.
The AES is capable of using cryptographic keys of 128/192/256 bits to encrypt and decrypt data in blocks of 128
bits. This 128-bit/192-bit/256-bit key is defined in the AES_KEYWRx.
The input to the encryption processes of the CBC, CFB, and OFB modes includes, in addition to the plaintext, a
128-bit data block called the initialization vector (IV), which must be set in the AES_IVRx. The initialization vector
is used in an initial step in the encryption of a message and in the corresponding decryption of the message. The
AES_IVRx are also used by the CTR mode to set the counter value.
50.4.1 Operation Modes
The AES supports the following modes of operation:
 ECB: Electronic Code Book
 CBC: Cipher Block Chaining
 OFB: Output Feedback
 CFB: Cipher Feedback
̶ CFB8 (CFB where the length of the data segment is 8 bits)
̶ CFB16 (CFB where the length of the data segment is 16 bits)
̶ CFB32 (CFB where the length of the data segment is 32 bits)
̶ CFB64 (CFB where the length of the data segment is 64 bits)
̶ CFB128 (CFB where the length of the data segment is 128 bits)
 CTR: Counter
 GCM: Galois/Counter Mode
The data pre-processing, post-processing and data chaining for the concerned modes are automatically
performed. Refer to the NIST Special Publication 800-38A and NIST Special Publication 800-38D for more
complete information.
These modes are selected by setting the OPMOD field in the AES_MR.
1588
SAMA5D4 Series [DATASHEET]
Atmel-11238A-ATARM-SAMA5D4-Datasheet_30-Sep-14