SAMA5D44_14 Datasheet, PDF (1122/1776 Pages) ATMEL Corporation – Atmel | SMART ARM-based Embedded MPU

38.14.2 HSMCI Mode Register
Name:
Address:
Access:
HSMCI_MR
0xF8000004 (0), 0xFC000004 (1)
Read/Write
31
30
29
28
27
26
–
–
–
–
–
–
23
22
21
20
19
18
–
–
–
–
–
–
15
14
13
12
11
10
–
PADV
FBYTE
WRPROOF RDPROOF
7
6
5
4
3
2
CLKDIV
25
–
17
–
9
PWSDIV
1
24
–
16
CLKODD
8
0
This register can only be written if the WPEN bit is cleared in the HSMCI Write Protection Mode Register.
• CLKDIV: Clock Divider
High Speed MultiMedia Card Interface clock (MCCK or HSMCI_CK) is Master Clock (MCK) divided by
({CLKDIV,CLKODD}+2).
• PWSDIV: Power Saving Divider
High Speed MultiMedia Card Interface clock is divided by 2^(PWSDIV) + 1 when entering Power Saving Mode.
Warning: This value must be different from 0 before enabling the Power Save Mode in the HSMCI_CR (HSMCI_PWSEN
bit).
• RDPROOF: Read Proof Enable
Enabling Read Proof allows to stop the HSMCI Clock during read access if the internal FIFO is full. This will guarantee data
integrity, not bandwidth.
0: Disables Read Proof.
1: Enables Read Proof.
• WRPROOF: Write Proof Enable
Enabling Write Proof allows to stop the HSMCI Clock during write access if the internal FIFO is full. This will guarantee
data integrity, not bandwidth.
0: Disables Write Proof.
1: Enables Write Proof.
• FBYTE: Force Byte Transfer
Enabling Force Byte Transfer allow byte transfers, so that transfer of blocks with a size different from modulo 4 can be
supported.
Warning: BLKLEN value depends on FBYTE.
0: Disables Force Byte Transfer.
1: Enables Force Byte Transfer.
1122
SAMA5D4 Series [DATASHEET]
Atmel-11238A-ATARM-SAMA5D4-Datasheet_30-Sep-14