SAMA5D44_14 Datasheet, PDF (1271/1776 Pages) ATMEL Corporation – Atmel | SMART ARM-based Embedded MPU

42.5.1 Baud Rate Generator
The baud rate generator provides the bit period clock named baud rate clock to both the receiver and the
transmitter.
The baud rate clock is the peripheral clock divided by 16 times the value (CD) written in the Debug Unit Baud Rate
Generator register (DBGU_BRGR). If DBGU_BRGR is set to 0, the baud rate clock is disabled and the Debug
Unit's UART remains inactive. The maximum allowable baud rate is peripheral clock divided by 16. The minimum
allowable baud rate is peripheral clock divided by (16 x 65536).
Baud Rate = ^f---p--^e--1^r--ⁱ-6^p---^h-_×-^e--^r--^a_C--^l--D^c---^l-^o--^c--^k-
Figure 42-3. Baud Rate Generator
Peripheral
clock
CD
CD
16-bit Counter
OUT
>1
1
0
0
Divide
by 16
Baud Rate
Clock
Receiver
Sampling Clock
42.5.2 Receiver
42.5.2.1 Receiver Reset, Enable and Disable
After device reset, the Debug Unit receiver is disabled and must be enabled before being used. The receiver can
be enabled by writing one to the RXEN bit in the Debug Unit Control register (DBGU_CR). At this command, the
receiver starts looking for a start bit.
The programmer can disable the receiver by writing a one to the RXDIS bit in the DBGU_CR. If the receiver is
waiting for a start bit, it is immediately stopped. However, if the receiver has already detected a start bit and is
receiving the data, it waits for the stop bit before actually stopping its operation.
The programmer can also put the receiver in its reset state by writing a one to the RSTRX bit in the DBGU_CR. In
doing so, the receiver immediately stops its current operations and is disabled, whatever its current state. If
RSTRX is applied when data is being processed, this data is lost.
42.5.2.2 Start Detection and Data Sampling
The Debug Unit only supports asynchronous operations, and this affects only its receiver. The Debug Unit receiver
detects the start of a received character by sampling the DRXD signal until it detects a valid start bit. A low level
(space) on DRXD is interpreted as a valid start bit if it is detected for more than 7 cycles of the sampling clock,
which is 16 times the baud rate. Hence, a space that is longer than 7/16 of the bit period is detected as a valid start
bit. A space which is 7/16 of a bit period or shorter is ignored and the receiver continues to wait for a valid start bit.
When a valid start bit has been detected, the receiver samples the DRXD at the theoretical midpoint of each bit. It
is assumed that each bit lasts 16 cycles of the sampling clock (1-bit period) so the bit sampling point is eight cycles
(0.5-bit period) after the start of the bit. The first sampling point is therefore 24 cycles (1.5-bit periods) after the
falling edge of the start bit was detected.
Each subsequent bit is sampled 16 cycles (1-bit period) after the previous one.
SAMA5D4 Series [DATASHEET]
Atmel-11238A-ATARM-SAMA5D4-Datasheet_30-Sep-14
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