SAMA5D44_14 Datasheet, PDF (222/1776 Pages) ATMEL Corporation – Atmel | SMART ARM-based Embedded MPU

Figure 20-4. Wake-up Reset
SLCK
MCK
Main Supply
POR output
backup_nreset
proc_nreset
RSTTYP
periph_nreset
Resynch.
2 cycles
Processor Startup
XXX
Any
Freq.
0x1 = WakeUp Reset
XXX
4 cycles
20.4.3.3 User Reset
The User Reset is entered when a low level is detected on the NRST pin and the bit URSTEN in RSTC_MR is at 1.
The NRST input signal is resynchronized with SLCK to ensure proper behavior of the system.
The Processor Reset and the Peripheral Reset are asserted.
The User Reset is left when NRST rises, after a two-cycle resynchronization time and a 2-cycle processor startup.
The processor clock is re-enabled as soon as NRST is confirmed high.
When the processor reset signal is released, the RSTTYP field of the RSTC_SR is loaded with the value 0x4,
indicating a User Reset.
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SAMA5D4 Series [DATASHEET]
Atmel-11238A-ATARM-SAMA5D4-Datasheet_30-Sep-14