X2P376 Datasheet, PDF (7/14 Pages) AMI SEMICONDUCTOR – 0.15mm Structured ASIC

XPressArray-II 0.15mm Structured ASIC
Data Sheet
Table 4: Block RAM Configurations
Name
ra16_1_1_c
ra16_1_2_c
ra16_1_4_c
ra16_1_9_c
ra16_1_18_c
ra16_1_36_c
ra16_2_2_c
ra16_2_4_c
ra16_2_9_c
ra16_2_18_c
ra16_2_36_c
ra16_4_4_c
ra16_4_9_c
ra16_4_18_c
ra16_4_36_c
ra16_9_9_c
ra16_9_18_c
ra16_9_36_c
ra16_18_18_c
ra16_18_36_c
ra16_36_36_c
Port A
Depth
Data Parity
Width Width
16,384 1 N/A
16,384 1 N/A
16,384 1 N/A
16,384 1 N/A
16,384 1 N/A
16,384 1 N/A
8,192 2 N/A
8,192 2 N/A
8,192 2 N/A
8,192 2 N/A
8,192 2 N/A
4,096 4 N/A
4,096 4 N/A
4,096 4 N/A
4,096 4 N/A
2,048 8
1
2,048 8
1
2,048 8
1
1,024 16
2
1,024 16
2
512
32
4
Port B
Depth Width
16,384 1
8,192
2
4,096
4
2,048
8
1,024 16
512
32
8,192
2
4,096
4
2,048
8
1,024 16
512
32
4,096
4
2,048
8
1,024 16
512
32
2,048
8
1,024 16
512
32
2,048
8
1,024 16
512
32
Parity
Width
N/A
N/A
N/A
1
2
4
N/A
N/A
1
2
4
N/A
1
2
4
1
2
4
2
4
4
7.0 Delay-Locked Loop (DLL) Description
XPressArray-II devices employ clock tree synthesis, enabling
an unlimited number of clock and reset signals to be routed.
Synthesized clock trees deliver high speed clock signals with
minimal skew and power.
The XPressArray-II DLL (Figure 6) is an all digital clock
management function embedded into the XPressArray-II
bases. DLLs may be used to minimize clock insertion delay,
Table 5: Predefined Distributed RAMs
Name
xram16x1pc
xram16x2pc
xram16x4pc
xram16x8pc
xram16x10pc
xram16x16pc
xram16x18pc
xram16x32pc
xram32x1pc
xram32x2pc
xram32x4pc
xram32x8pc
xram32x10pc
xram32x16pc
xram32x18pc
xram32x32pc
Depth
16
16
16
16
16
16
16
16
32
32
32
32
32
32
32
32
Width
1
2
4
8
10
16
18
32
1
2
4
8
10
16
18
32
perform basic clock frequency synthesis and generate phase
shifts. The DLL provides both coarse and fine-grained phase
shifting with dynamic phase shift control. The quadrature clock
generation features deliver accurate clock phases at the load,
compensating for clock tree delays across the full range of
temperature and voltage. In clock divider and clock doubling
applications, duty cycle correction is available. A robust real-
time lock detection circuit completes the DLL.
CLKREF
PD
Delay Line
Control
DLL
AMI Semiconductor - Preliminary
www.amis.com
Figure 6: DLL
7
CLK360
FB360
CLK270
FB270
CLK180
FB180
CLK90
FB90
CLKDV
CLK2X
Clk Tree
Clk Tree
Clk Tree
Clk Tree