X2P376 Datasheet, PDF (5/14 Pages) AMI SEMICONDUCTOR – 0.15mm Structured ASIC

XPressArray-II 0.15mm Structured ASIC
Data Sheet
Table 3: Supported I/O Standards
I/O Standard
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
PCI33_3
PCI66
PCI-X 133
PCI-X 2.0 Mode 1
PCI-X 2.0 Mode 2
GTL
GTL+
SSTL2 Class I
SSTL2 Class II
HSTL18 Class I
HSTL18 Class II
HSTL18 Class III
HSTL18 Class IV
HSTL15 Class I
HSTL15 Class II
HSTL15 Class III
HSTL15 Class IV
LVPECL (input)
LVDS33
LVDS25
VCCO
3.3V
3.3V
2.5V
1.8V
1.5V
3.3V
3.3V
3.3V
3.3V
1.5V
N/A
N/A
2.5V
2.5V
1.8V
1.8V
1.8V
1.8V
1.5V
1.5V
1.5V
1.5V
3.3V
3.3V
2.5V
VCCAUX
3.3V
3.3V
3.3V
Output Termination
DCI Series Out 25W/50W
DCI Series Out 25W/50W
DCI Series Out 25W/50W
DCI Series Out 25W/50W
DCI Series Out 25W/50W
Input Termination
DCI Parallel Out 50W
DCI Parallel Out 50W
DCI Parallel Out 25W
DCI Parallel Out 25W
DCI Split Parallel in 114W
DCI Split Parallel in 100W
DCI Split Parallel in 100W
DCI Split Parallel in 100W
DCI Split Parallel in 100W
DCI Parallel in 50W
DCI Parallel in 50W
DCI Split Parallel in 100W
DCI Split Parallel in 100W
DCI Parallel in 50W
DCI Parallel in 50W
100W Differential Input
100W Differential Input
100W Differential Input
Performance
125MHz
125MHz
125MHz
125MHz
125MHz
33MHz
66MHz
133MHz
133MHz
266/533Mbps
100MHz
200MHz
400Mbps
400Mbps
500Mbps
500Mbps
500Mbps
500Mbps
500Mbps
500Mbps
500Mbps
500Mbps
1Gbps
1Gbps
1Gbps
Notes
2-24mA
2-24mA
2-24mA, 3.3V Tolerant
2-16mA, 3.3V Tolerant
2-16mA, 3.3V Tolerant
Input DDR Block
Register
Register
OEN DDR Block
IN
Latch
IN_DLY
Register
Register
0
MUX
1
OEN
DCI_CNTL
Output DDR Block
DCI
Register
Register
0
MUX
1
OUT
VREF
VCC
PullUp
Bus
Hold
PAD
ESD
PullDn
GND
Figure 4: Dual Data Rate (DDR) I/O Architecture
AMI Semiconductor - Preliminary
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