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X2P376 Datasheet, PDF (1/14 Pages) AMI SEMICONDUCTOR – 0.15mm Structured ASIC
XPressArray-II 0.15mm Structured ASIC
Data Sheet
1.0 Key Features
• Next-generation 0.15mm hybrid structured ASIC
• Platform for high-performance 1.5V/1.2V ASICs and FPGA-
to-ASIC conversions
• NRE and production cost savings
• Significant time-to-market advantages
• Drop-in replacement for cost-reducing Xilinx® Virtex-II and
Virtex-II Pro and Altera® APEX-II and Stratix designs
• 417K to 3.9M ASIC gates
• 210MHz system, 500MHz local clock speeds
• Low power consumption (0.055mW/MHz/gate @ 1.575V)
• 332Kbits to 4.8Mbits of block RAM memory
• Up to 5.6Mbits of memory when 50 percent of the logic sites
are used for distributed memory
• 18Kbit initializable dual-port RAM blocks at speeds up to
330MHz
• Flexible I/O technology, any I/O standard assigned to any I/O
pin
• Initializable distributed memory at speeds up to 210MHz
• Configurable signal, core and I/O power supply pin locations
• Supports LVTTL, LVCMOS, PCI33, PCI66, PCI-X 133, PCI-X
2.0, GTL/+, HSTL class 1, 2, 3, and 4, SSTL2 class 1 and 2,
LVPECL (input), LVDS I/O standards
• 1.5V, 1.8V, 2.5V, and 3.3V capable I/O
• True 3.3V tolerance with no external resistor necessary
• Digital controlled impedance
• Built-in DDR support
• LVDS data rates to 1Gbps
• Up to 1346 user I/Os
• Comprehensive clock management circuitry
• Up to eight DLLs and eight PLLs
• Variety of package options
• Integrated high-fault coverage scan-test, memory BIST and
JTAG
2.0 Product Description
Targeted at medium-density, high-speed, 1.5V and 1.2V ASIC
applications and high-density FPGA-to-ASIC conversions, the
XPressArray™-II 0.15mm hybrid structured ASIC is an
innovative next-generation technology platform that reduces
time-to-market for system-on-chip (SoC) applications while
delivering significant NRE and unit cost savings.
XPressArray-II offers a true drop-in replacement for Xilinx
Virtex-II, Virtex-II Pro, Altera APEX-II, and Stratix FPGAs,
making it the industry's lowest cost ASIC conversion solution.
The result is a simplified route to cost reductions for OEMs
looking to combine the flexibility of FPGA prototyping with a
path to an ASIC for final production.
Table 1 shows the seven bases of the AMIS XPressArray-II
family. These bases offer between 417K and 3.9M gates.
Configurable memory ranges from 332Kbits to 4.8Mbits, which
increases to 5.6Mbits of memory with the addition of
distributed configurable memory, assuming 50 percent of the
logic sites are used for memory. Individual memories may
be configured as single or dual port with asymmetrical port widths.
The architecture also supports memory initialization.
Flexible I/O technology includes support for a comprehensive
array of common standards and compatibility with 1.5V, 1.8V,
2.5V, and 3.3V I/O schemes. I/O power supply banking
supports the operating voltage requirements of multiple I/O
standards on the same device. Each XPressArray-II I/O may
be configured to support LVTTL, LVCMOS, PCI33, PCI66,
PCI-X 133, PCI-X 2.0, GTL/+, HSTL class 1, 2, 3, and 4,
SSTL2 class 1 and 2, LVPECL input, and LVDS. I/Os support
digital controlled impedance (DCI) on-chip termination. Dual
data rate (DDR) support for high-speed memory interface is
built in.
Table 1: XPressArray-II 0.15mm Hybrid Structured ASIC Family
XPressArray-II Base
X2P376
X2P528
X2P680
X2P846
X2P998
X2P1148
X2P1346
18K RAM Blocks
18
40
57
101
145
189
264
(1) Usable 2RW RAM bits
(2) Usable 2-NAND equivalent logic gates
No Distributed RAM
Bits(K)1
Gates(K)2
332
417
737
650
1051
1203
1862
1629
2673
2196
3484
2902
4866
3929
50% Distributed RAM
Bits(K)1
Gates(K)2
415
209
867
325
1291
602
2188
815
3112
1098
4064
1451
5652
1965
DLL
2
2
4
4
4
8
8
PLL User I/Os
4
376
4
528
4
680
4
846
4
998
8
1148
8
1346
AMI Semiconductor - Preliminary
www.amis.com
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