X2P376 Datasheet, PDF (12/14 Pages) AMI SEMICONDUCTOR – 0.15mm Structured ASIC

XPressArray-II 0.15mm Structured ASIC
Table 9: DLL Specifications
Parameter
Operating Modes
Low/High Frequency Operation
Control Inputs
Available Outputs
Frequency Range
Clock Doubler Frequency Range
Clock Divider Range
Duty Cycle Correction Resolution
Fine Quadrature Phase Shift Range
Clock Tree Delay Compensation
Output Clock Jitter CLKO (Peak-to-Peak)
Output Clock Jitter CLK90, CLK180, CLK270 (Peak-to-Peak)
Output Clock Jitter CLK2X (Peak-to-Peak)
Output Clock Jitter CLKDV (Integer Division, Peak-to-Peak)
Output Clock Jitter CLKDV (Non-integer Division, Peak-to-Peak)
Output Clock Phase Offset (Between all Quadratures)
Lock Time
Value
• Clock Tree
• Zero Delay Buffer
• External Feedback
• Quadrature Shift
• Basic Frequency Shift
Combined
DCC (Duty Cycle Correction), TIMELOCK
CLK90, CLK180, CLK270, CLK360,
CLKDV, CLK2X, LOCK, VALIDCLK
25-300MHz
50-500MHz
1.6-16 in 0.5 steps, 16-32 in 1.0 steps
45-55%
+/- 64 taps (@ Typical 1 Tap = 70ps)
Yes
+/- 175ps
+/- 250ps
+/- 325ps
+/- 250ps
+/- 400ps
+/- 250ps
180us @ 20MHz
40us @ >60MHz
Table 10: PLL Specifications
Parameter
Operating Modes
Input Frequency Range
Input Duty Cycle
Input Jitter (Peak-to-Peak)
PFD Frequency Range
VCO Frequency Range
Output Frequency Range
Output Duty Cycle
Output Period Jitter (Peak-to-Peak)
Reference Divider
Feedback Divider
Post Dividers
Phase Shift Resolution
Phase Shift Range
Available Outputs
General Purpose Mode
• Normal with Phase Shift
• Zero Delay Buffer
• External Feedback
• Clock Tree
1.5-620MHz
40-60%
2% of input period
1-50MHz
200-500MHz
1-500MHz
45-55%
200ps
1-2049
1-2049
1-2049
1/[Fvco*5]
0-360°
FOUTA, FOUTB
LVDS Mode
• LVDS
1.5-620MHz
40-60%
2% of input period
1-50MHz
200-1000MHz
1-800MHz
45-55%
175ps
1-2049
1-33
N/A
1/[Fvco*5]
0-360°
FOUT90, FOUT180, FOUT270, FOUT360
Electrical specifications subject to change without notice.
Data Sheet
AMI Semiconductor - Preliminary
www.amis.com
12