405GP Datasheet, PDF (53/59 Pages) Applied Micro Circuits Corporation – Power PC 405GP Embedded Processor

Revision 2.03 – September 7, 2007
Data Sheet
405GP – Power PC 405GP Embedded Processor
I/O Specifications—133 and 200MHz
Notes:
1. The SDRAM command interface is configurable through SDRAM0_TR[LDF] to provide a 2 to 4 cycle delay before the
command is used by SDRAM.
2. SDRAM I/O timings are specified relative to a MemClkOut terminated into a lumped 10pF load.
3. SDRAM interface hold times are guaranteed at the PPC405GP package pin. System designers must use the PPC405GP
IBIS model (available from www.amcc.com) to ensure their clock distribution topology minimizes loading and reflections,
and that the relative delays on clock wiring do not exceed the delays on other SDRAM signal wiring.
4. PerClk rising edge at package pin with a 10pF load trails the internal PLB clock by approximately 0.8ns.
5. I/O H is specified at 2.4 V and I/O L is specified at 0.4 V.
Input (ns)
Signal
Setup Time Hold Time
(T_IS min) (T_IH min)
SDRAM Interface
BA1:0
na
na
BankSel3:0
na
na
CAS
na
na
ClkEn0:1
na
na
DQM0:3
na
na
DQMCB
na
na
ECC0:7
2
1
MemAddr12:0
na
na
MemData0:31
2
1
RAS
na
na
WE
na
na
External Slave Peripheral Interface
DMAAck0:3
na
na
DMAReq0:3
5
1
EOT0:3/TC0:3
dc
dc
PerAddr0:31
4
1
PerBLast
4
1
PerCS0
na
na
PerCS1:7[GPIO10:16]
PerData0:31
6
1
PerOE
na
na
PerPar0:3
4
1
PerR/W
4
1
PerReady
9
1
PerWBE0:3
3
1
External Master Peripheral Interface
BusReq
na
na
ExtAck
na
na
ExtReq
5
1
ExtReset
na
na
HoldAck
na
na
HoldPri
4
1
HoldReq
5
1
PerClk
na
na
PerErr
3
1
Output (ns)
Valid Delay Hold Time
(T_OV max) (T_OH min)
7.5
1
6.2
1
7.5
1
5.2
1
6.1
1
6.2
1
6.2
1
7.6
1
6.3
1
7.5
1
7.5
1
8
0
na
na
8
0
10
0
8
0
8
0
10
0
8
0
10
0
8
0
na
na
8
0
8
0
7
0
na
na
8
0
8
0
na
na
na
na
0.9
0.7
na
na
Output Current (mA)
I/O H
I/O L
(minimum) (minimum)
Clock
Notes
19
12
MemClkOut 1, 2
19
12
MemClkOut
2
19
12
MemClkOut 1, 2
40
25
MemClkOut
2
19
12
MemClkOut
2
19
12
MemClkOut
2
19
12
MemClkOut
2
19
12
MemClkOut 1, 2
19
12
MemClkOut
2
19
12
MemClkOut 1, 2
19
12
MemClkOut 1, 2
12
8
PerClk
na
na
PerClk
12
8
PerClk
19
12
PerClk
12
8
PerClk
12
8
PerClk
19
12
PerClk
12
8
PerClk
19
12
PerClk
12
8
PerClk
na
na
PerClk
12
8
PerClk
12
8
PerClk
12
8
PerClk
na
na
PerClk
19
12
PerClk
12
8
PerClk
na
na
PerClk
na
na
PerClk
19
12
PLB Clk
4
na
na
PerClk
AMCC
53