405GP Datasheet, PDF (49/59 Pages) Applied Micro Circuits Corporation – Power PC 405GP Embedded Processor

Revision 2.03 – September 7, 2007
Data Sheet
405GP – Power PC 405GP Embedded Processor
Peripheral Interface Clock Timings
Parameter
Min
Max
Units
PCIClk input frequency (asynchronous mode)
Note 1
66.66
MHz
PCIClk period (asynchronous mode)
15
Note 1
ns
PCI Clock frequency (synchronous mode)
25
33.33
MHz
PCI Clock period (synchronous mode - Note 2)
30
40
ns
PCIClk input high time
40% of nominal period 60% of nominal period
ns
PCIClk input low time
40% of nominal period 60% of nominal period
ns
EMCMDClk output frequency
–
2.5
MHz
EMCMDClk period
400
–
ns
EMCMDClk output high time
160
–
ns
EMCMDClk output low time
160
–
ns
PHYTxClk input frequency
2.5
25
MHz
PHYTxClk period
40
400
ns
PHYTxClk input high time
35% of nominal period
–
ns
PHYTxClk input low time
35% of nominal period
–
ns
PHYRxClk input frequency
2.5
25
MHz
PHYRxClk period
40
400
ns
PHYRxClk input high time
35% of nominal period
–
ns
PHYRxClk input low time
35% of nominal period
–
ns
PerClk output frequency–133MHz
–
33.33
MHz
PerClk period–133MHz
30
–
ns
PerClk output frequency–200MHz
–
50
MHz
PerClk period–200MHz
20
–
ns
PerClk output frequency–266MHz
–
66.66
MHz
PerClk period–266MHz
15
–
ns
PerClk output high time
45% of nominal period 55% of nominal period
ns
PerClk output low time
45% of nominal period 55% of nominal period
ns
PerClk clock edge stability (phase jitter, cycle to cycle)
± 0.3
ns
UARTSerClk input frequency (Note 3)
–
1000/(2T_OPB+2ns)
MHz
UARTSerClk period
2T_OPB+2
–
ns
UARTSerClk input high time
T_OPB+1
–
ns
UARTSerClk input low time
T_OPB+1
–
ns
TmrClk input frequency–133MHz
–
33.33
MHz
TmrClk period–133MHz
30
–
ns
TmrClk input frequency–200MHz
–
50
MHz
TmrClk period–200MHz
20
–
ns
TmrClk input frequency–266MHz
–
66.66
MHz
TmrClk period–266MHz
15
–
ns
TmrClk input high time
40% of nominal period 60% of nominal period
ns
TmrClk input low time
40% of nominal period 60% of nominal period
ns
Note:
1. In asynchronous PCI mode the minimum PCIClk frequency is 1/8 the PLB Clock. Refer to the PowerPC 405GP Embedded Processor
User’s Manual for more information.
2. In synchronous PCI mode the PCI clock is derived from SysClk and the PCIClk input pin is unused.
3. T_OPB is the period in ns of the OPB clock. The maximum OPB clock frequency is 50 MHz for 200MHz parts and 66.66MHz for 266MHz
parts.
AMCC
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