405GP Datasheet, PDF (39/59 Pages) Applied Micro Circuits Corporation – Power PC 405GP Embedded Processor

Revision 2.03 – September 7, 2007
Data Sheet
405GP – Power PC 405GP Embedded Processor
Signal Functional Description (Part 5 of 8)
Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball.
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 34 for recommended termination values.
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 34 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
7. Pull-up may be required. See “External Bus Control Signals” on page 34.
Signal Name
Description
I/O
External Master Peripheral Interface
PerClk
Peripheral clock to be used by an external master and by
synchronous peripheral slaves.
O
ExtReset
Peripheral reset to be used by an external master and by
synchronous peripheral slaves.
O
HoldReq
Hold Request, used by an external master to request ownership of
the peripheral bus.
I
HoldAck
Hold Acknowledge, used by the PPC405GP to transfer ownership of
peripheral bus to an external master.
O
ExtReq
ExtReq is used by an external master to indicate it is prepared to
transfer data.
I
ExtAck
ExtAck is used by the PPC405GP to indicate a data transfer cycle.
O
HoldPri
Used by an external master to indicate the priority of a given external
master tenure.
I
BusReq
Used when the PPC405GP needs to regain control of peripheral
interface from an external master.
O
PerErr
An input used to indicate to the PPC405GP that an external slave
peripheral error occurred.
I
Internal Peripheral Interface
UARTSerClk
Serial Clock used to provide an alternate clock to the internally
generated serial clock. Used in cases where the allowable internally
generated baud rates are not satisfactory. This input can be
I
individually connected to either UART.
UART0_Rx
UART0 Serial Data In.
I
UART0_Tx
UART0 Serial Data Out.
O
UART0_DCD
UART0 Data Carrier Detect.
I
UART0_DSR
UART0 Data Set Ready.
I
UART0_CTS
UART0 Clear To Send.
I
UART0_DTR
UART0 Data Terminal Ready.
O
UART0_RTS
UART0 Request To Send.
O
UART0_RI
UART0 Ring Indicator.
I
UART1_Rx
UART1 Serial Data In.
I
Type
5V tolerant
3.3V LVTTL
5V tolerant
3.3V LVTTL
5V tolerant
3.3V LVTTL
5V tolerant
3.3V LVTTL
5V tolerant
3.3V LVTTL
5V tolerant
3.3V LVTTL
5V tolerant
3.3V LVTTL
5V tolerant
3.3V LVTTL
5V tolerant
3.3V LVTTL
5V tolerant
3.3V LVTTL
5V tolerant
3.3V LVTTL
5V tolerant
3.3V LVTTL
5V tolerant
3.3V LVTTL
5V tolerant
3.3V LVTTL
5V tolerant
3.3V LVTTL
5V tolerant
3.3V LVTTL
5V tolerant
3.3V LVTTL
5V tolerant
3.3V LVTTL
5V tolerant
3.3V LVTTL
Notes
1, 5
6
1
6
1
1, 5
1
1
6
1
1
1
6
6
1
1
AMCC
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