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405GP Datasheet, PDF (46/59 Pages) Applied Micro Circuits Corporation – Power PC 405GP Embedded Processor
405GP – Power PC 405GP Embedded Processor
Revision 2.03 – September 7, 2007
Data Sheet
DC Electrical Characteristics
Parameter
Symbol
Typical
Maximum
Unit
Active Operating Current (VDD)–133MHz
IDD
TBD
TBD
mA
Active Operating Current (VDD)–200MHz
IDD
550
670
mA
Active Operating Current (VDD)–266 MHz
IDD
730
880
mA
Active Operating Current (OVDD)–133MHz
IODD
TBD
TBD
mA
Active Operating Current (OVDD)–200MHz
IODD
35
37
mA
Active Operating Current (OVDD)–266 MHz
IODD
37
40
mA
PLL VDD Input current
IPLL
16
23
mA
Active Operating Power–133MHz
PDD
TBD
TBD
W
Active Operating Power–200MHz
PDD
1.5
2.01
W
Active Operating Power–266MHz
PDD
2.0
2.61
W
Note:
1. Maximum power is characterized at VDD = +2.7V, OVDD = +3.6V, TC = +85°C, across the silicon process (worse case to best case),
while running an application designed to maximize power consumption. The specifications at 200MHz correspond to CPU = 200 MHz,
PLB = 100MHz, OPB = EBC = 50MHz, PCI = 33.3MHz. The specifications at 266MHz correspond to CPU = 266.6MHz, PLB
=133.3MHz, OPB = EBC = 66.6MHz, and PCI = 33.3MHz.
2. AVDD should be derived from VDD using the following circuit:
VDD
L1
+
AVDD
L1 – 2.2μH SMT inductor (equivalent to MuRata
LQH3C2R2M34) or SMT chip ferrite bead (equivalent
to MuRata BLM31A700S)
C1
C2
C3
C1 – 3.3 μF SMT tantalum
AGND C2 – 0.1μF SMT monolithic ceramic capacitor with X7R
dielectric or equivalent
GND
C3 – 0.01 μF SMT monolithic ceramic capacitor with X7R
dielectric or equivalent
Test Conditions
Clock timing and switching characteristics are specified in accordance with
Output
operating conditions shown in the table “Recommended DC Operating
Pin
Conditions.” For all signals other than PCI signals, AC specifications are
50 pF
characterized at OVDD = +3V and TC = +85°C with the 50pF test load
All signals other
than PCI
shown in the figure at right.
For PCI signals there are two different test load circuits, one for the rising
edge and one the falling edge as shown in the figures at right.
Output
Pin
PCI Rising edge
10 pF
25 Ω
Output
Pin
PCI Falling edge
OVDD
25 Ω
10 pF
46
AMCC