405GP Datasheet, PDF (40/59 Pages) Applied Micro Circuits Corporation – Power PC 405GP Embedded Processor

405GP – Power PC 405GP Embedded Processor
Revision 2.03 – September 7, 2007
Data Sheet
Signal Functional Description (Part 6 of 8)
Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball.
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 34 for recommended termination values.
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 34 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
7. Pull-up may be required. See “External Bus Control Signals” on page 34.
Signal Name
UART1_Tx
UART1_DSR/
UART1_CTS
UART1_RTS/
UART1_DTR
IICSCL
IICSDA
Interrupts Interface
IRQ0:6[GPIO17:23]
JTAG Interface
TDI
TMS
TDO
TCK
TRST
System Interface
SysClk
SysReset
AV_DD
SysErr
Halt
Description
I/O
UART1 Serial Data Out.
O
UART1 Data Set Ready
or
I
UART1 Clear To Send. To access this function, software must toggle
a DCR bit.
UART1 Request To Send
or
O
UART1 Data Terminal Ready. To access this function, software must
toggle a DCR bit.
IIC Serial Clock.
I/O
IIC Serial Data.
I/O
Type
5V tolerant
3.3V LVTTL
5V tolerant
3.3V LVTTL
5V tolerant
3.3V LVTTL
5V tolerant
3.3V LVTTL
5V tolerant
3.3V LVTTL
Interrupt requests
or
General Purpose I/O. To access this function, software must toggle a
DCR bit.
I[I/O]
5V tolerant
3.3V LVTTL
Test data in.
JTAG test mode select.
Test data out.
JTAG test clock. The frequency of this input can range from DC to
25 MHz.
JTAG reset. TRST must be low at power-on to initialize the JTAG
controller and for normal operation of the PPC405GP.
I
5V tolerant
3.3V LVTTL
I
5V tolerant
3.3V LVTTL
O
5V tolerant
3.3V LVTTL
I
5V tolerant
3.3V LVTTL
I
5V tolerant
3.3V LVTTL
Main system clock input.
I
Main system reset. External logic can drive this bidirectional pin low
(minimum of 16 cycles) to initiate a system reset. A system reset can
also be initiated by software. Implemented as an open-drain output
I/O
(two states; 0 or open circuit).
Clean voltage input for the PLL.
I
Set to 1 when a Machine Check is generated.
O
Halt from external debugger.
I
5V tolerant
3.3V LVTTL
5V tolerant
3.3V LVTTL
5V tolerant
3.3V LVTTL
5V tolerant
3.3V LVTTL
Notes
6
1
6
1, 2
1, 2
1
1, 4
1, 4
1, 4
5
1, 2
1, 2
40
AMCC