405GP Datasheet, PDF (37/59 Pages) Applied Micro Circuits Corporation – Power PC 405GP Embedded Processor

Revision 2.03 – September 7, 2007
Data Sheet
405GP – Power PC 405GP Embedded Processor
Signal Functional Description (Part 3 of 8)
Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball.
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 34 for recommended termination values.
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 34 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
7. Pull-up may be required. See “External Bus Control Signals” on page 34.
Signal Name
Description
I/O
SDRAM Interface
Memory data bus.
Notes:
MemData0:31
1. MemData0 is the most significant bit (msb).
I/O
2. MemData31 is the least significant bit (lsb).
Memory address bus.
Notes:
MemAddr12:0
O
1. MemAddr12 is the most significant bit (msb).
2. MemAddr0 is the least significant bit (lsb).
BA1:0
Bank Address supporting up to 4 internal banks.
O
RAS
Row Address Strobe.
O
CAS
Column Address Strobe.
O
DQM for byte lane: 0 (MemData0:7),
DQM0:3
1 (MemData8:15),
2 (MemData16:23), and
O
3 (MemData24:31)
DQMCB
DQM for ECC check bits.
O
ECC0:7
ECC check bits 0:7.
I/O
BankSel0:3
Select up to four external SDRAM banks.
O
WE
Write Enable.
O
ClkEn0:1
SDRAM Clock Enable.
O
MemClkOut0:1
Two copies of an SDRAM clock allows, in some cases, glueless
SDRAM attach without requiring this signal to be repowered by a PLL O
or zero-delay buffer.
External Slave Peripheral Interface
PerData0:31
Peripheral data bus used by PPC405GP when not in external master
mode, otherwise used by external master.
I/O
Note: PerData0 is the most significant bit (msb) on this bus.
PerAddr0:31
Peripheral address bus used by PPC405GP when not in external
master mode, otherwise used by external master.
I/O
Note: PerAddr0 is the most significant bit (msb) on this bus.
PerPar0:3
Peripheral byte parity signals.
I/O
PerWBE0:3
[PerWE]PCIINT
As outputs, these pins can act as byte-enables which are valid for an
entire cycle or as write-byte-enables which are valid for each byte on
each data transfer, allowing partial word transactions. As outputs,
pins are used by either the pripheral controller or the DMA controller
I/O
depending upon the type of transfer involved. Used as inputs when
an external bus master owns the external interface.
Peripheral write enable. Low when any of the four PerWBE0:3 write
byte enables are low.
or
O
PCI interrupt. Open-drain output (two states; 0 or open circuit)
Type
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
5V tolerant
3.3V LVTTL
5V tolerant
3.3V LVTTL
5V tolerant
3.3V LVTTL
5V tolerant
3.3V LVTTL
5V tolerant
3.3V PCI
Notes
1
1
1
1, 7
AMCC
37