405GP Datasheet, PDF (36/59 Pages) Applied Micro Circuits Corporation – Power PC 405GP Embedded Processor

405GP – Power PC 405GP Embedded Processor
Revision 2.03 – September 7, 2007
Data Sheet
Signal Functional Description (Part 2 of 8)
Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball.
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 34 for recommended termination values.
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 34 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
7. Pull-up may be required. See “External Bus Control Signals” on page 34.
Signal Name
PCIGnt0[Req]
PCIGnt1:5
Ethernet Interface
PHYRxD3:0
EMCTxD3:0
PHYRxErr
PHYRxClk
PHYRxDV
PHYCrS
EMCTxErr
EMCTxEn
PHYTxClk
Description
I/O
Gnt0 when internal arbiter is used
or
O
Req when external arbiter is used.
Used as PCIGnt1:5 output when internal arbiter is used.
O
Received data. This is a nibble wide bus from the PHY. The data is
synchronous with the PHYRxClk.
I
Transmit data. A nibble wide data bus towards the net. The data is
synchronous to the PHYTxClk.
O
Receive Error. This signal comes from the PHY and is synchronous
to the PHYRxClk.
I
Receiver Medium clock. This signal is generated by the PHY.
I
Receive Data Valid. Data on the Data Bus is valid when this signal is
activated. Deassertion of this signal indicates end of the frame
I
reception.
Carrier Sense signal from the PHY. This is an asynchronous signal.
I
Transmit Error. This signal is generated by the Ethernet controller, is
connected to the PHY and is synchronous with the PHYTxClk. It
O
informs the PHY that an error was detected.
Transmit Enable. This signal is driven by the EMAC to the PHY. Data
is valid during the active state of this signal. Deassertion of this signal
indicates end of frame transmission. This signal is synchronous to
O
the PHYTxClk.
This clock comes from the PHY and is the Medium Transmit clock.
I
PHYCol
Collision signal from the PHY. This is an asynchronous signal.
I
EMCMDClk
Management Data Clock. The MDClk is sourced to the PHY. This
clock has a period of 400ns, adjustable via EMAC0_STACR[OPBC].
Management information is transferred synchronously with respect to
O
this clock.
Management Data Input/Output is a bidirectional signal between the
EMCMDIO[PHYMDIO] Ethernet controller and the PHY. It is used to transfer control and
I/O
status information.
Type
5V tolerant
3.3V PCI
5V tolerant
3.3V PCI
5V tolerant
3.3V LVTTL
5V tolerant
3.3V LVTTL
5V tolerant
3.3V LVTTL
5V tolerant
3.3V LVTTL
5V tolerant
3.3V LVTTL
5V tolerant
3.3V LVTTL
5V tolerant
3.3V LVTTL
5V tolerant
3.3V LVTTL
5V tolerant
3.3V LVTTL
5V tolerant
3.3V LVTTL
5V tolerant
3.3V LVTTL
5V tolerant
3.3V LVTTL
Notes
1
6
1
1
1
1
6
6
1
1
1
36
AMCC