EPF6016ATI144-3N Datasheet, PDF (9/52 Pages) Altera Corporation – Programmable Logic Device Family

Figure 4. Logic Element
FLEX 6000 Programmable Logic Device Family Data Sheet
Carry-In Cascade-In
Register Bypass
Programmable
Register
data1
data2
data3
data4
Look-Up
Table
(LUT)
Carry
Chain
Cascade
Chain
PRN
DQ
CLRN
LE-Out
labctrl1
labctrl2
Chip-Wide Reset
labctrl3
labctrl4
Clear/ Preset
Logic
Clock
Select
Carry-Out Cascade-Out
The programmable flipflop in the LE can be configured for D, T, JK, or SR
operation. The clock and clear control signals on the flipflop can be driven
by global signals, general-purpose I/O pins, or any internal logic. For
combinatorial functions, the flipflop is bypassed and the output of the
LUT drives the outputs of the LE. The LE output can drive both the local
interconnect and the FastTrack Interconnect.
The FLEX 6000 architecture provides two types of dedicated high-speed
data paths that connect adjacent LEs without using local interconnect
paths: carry chains and cascade chains. A carry chain supports high-speed
arithmetic functions such as counters and adders, while a cascade chain
implements wide-input functions such as equivalent comparators with
minimum delay. Carry and cascade chains connect LEs 2 through 10 in an
LAB and all LABs in the same half of the row. Because extensive use of
carry and cascade chains can reduce routing flexibility, these chains
should be limited to speed-critical portions of a design.
Altera Corporation
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