EPF6016ATI144-3N Datasheet, PDF (29/52 Pages) Altera Corporation – Programmable Logic Device Family

FLEX 6000 Programmable Logic Device Family Data Sheet
The instruction register length for FLEX 6000 devices is three bits. Table 9
shows the boundary-scan register length for FLEX 6000 devices.
Table 9. FLEX 6000 Device Boundary-Scan Register Length
Device
EPF6010A
EPF6016
EPF6016A
EPF6024A
Boundary-Scan Register Length
522
621
522
666
FLEX 6000 devices include a weak pull-up on JTAG pins.
f See Application Note 39 (IEEE 1149.1 (JTAG) Boundary-Scan Testing in Altera
Devices) for more information.
Figure 16 shows the timing requirements for the JTAG signals.
Figure 16. JTAG Waveforms
TMS
TDI
TCK
TDO
Signal
to Be
Captured
Signal
to Be
Driven
t _JCP
t _JCH
t _JCL
t _JPSU
t_JPZX
t_JSSU
t_JPCO
t_JSH
t_JSZX
t_JSCO
t _JPH
t _JPXZ
t_JSXZ
Table 10 shows the JTAG timing parameters and values for FLEX 6000
devices.
Altera Corporation
29