EPF6016ATI144-3N Datasheet, PDF (18/52 Pages) Altera Corporation – Programmable Logic Device Family

FLEX 6000 Programmable Logic Device Family Data Sheet
The FastTrack Interconnect consists of column and row interconnect
channels that span the entire device. Each row of LABs is served by a
dedicated row interconnect, which routes signals between LABs in the
same row, and also routes signals from I/O pins to LABs. Additionally,
the local interconnect routes signals between LEs in the same LAB and in
adjacent LABs. The column interconnect routes signals between rows and
routes signals from I/O pins to rows.
LEs 1 through 5 of an LAB drive the local interconnect to the right, while
LEs 6 through 10 drive the local interconnect to the left. The DATA1 and
DATA3 inputs of each LE are driven by the local interconnect to the left;
DATA2 and DATA4 are driven by the local interconnect to the right. The
local interconnect also routes signals from LEs to I/O pins. Figure 9 shows
an overview of the FLEX 6000 interconnect architecture. LEs in the first
and last columns have drivers on both sides so that all LEs in the LAB can
drive I/O pins via the local interconnect.
Figure 9. FastTrack Interconnect Architecture
Row Interconnect (n Channels) (1)
5
To/From
10
Adjacent
LAB
10
2
5
22
2
5
55
5 10
20
5
10
10
LE 1
5
through
10
LE 5
10
5
LE 6
through
10
10
LE 10
2
5
22
2
5
55
5
10
20
5
10
10
LE 1
5
through
10
LE 5
10
5
LE 6
through
10
10
LE 10
10
To/From
5
Adjacent
10
LAB
Local Interconnect (32 Channels)
Column Interconnect (m Channels) (1)
Note:
(1) For EPF6010A, EPF6016, and EPF6016A devices, n = 144 channels and m = 20 channels; for EPF6024A devices,
n = 186 channels and m = 30 channels.
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Altera Corporation