EPF6016ATI144-3N Datasheet, PDF (30/52 Pages) Altera Corporation – Programmable Logic Device Family

FLEX 6000 Programmable Logic Device Family Data Sheet
Table 10. JTAG Timing Parameters & Values
Symbol
Parameter
t_JCP
t_JCH
t_JCL
t_JPSU
t_JPH
t_JPCO
t_JPZX
t_JPXZ
t_JSSU
t_JSH
t_JSCO
t_JSZX
t_JSXZ
TCK clock period
TCK clock high time
TCK clock low time
JTAG port setup time
JTAG port hold time
JTAG port clock-to-output
JTAG port high impedance to valid output
JTAG port valid output to high impedance
Capture register setup time
Capture register hold time
Update register clock-to-output
Update register high impedance to valid
output
Update register valid output to high
impedance
Min Max Unit
100
ns
50
ns
50
ns
20
ns
45
ns
25
ns
25
ns
25
ns
20
ns
45
ns
35
ns
35
ns
35
ns
Generic Testing
Each FLEX 6000 device is functionally tested. Complete testing of each
configurable SRAM bit and all logic functionality ensures 100%
configuration yield. AC test measurements for FLEX 6000 devices are
made under conditions equivalent to those shown in Figure 17. Multiple
test patterns can be used to configure devices during all stages of the
production flow.
Figure 17. AC Test Conditions
Power supply transients can affect
AC measurements. Simultaneous
transitions of multiple outputs
should be avoided for accurate
measurement. Threshold tests must
not be performed under AC conditions.
Large-amplitude, fast-ground-current
464 Ω
(703 Ω)
[521 Ω]
transients normally occur as the
Device
device outputs discharge the load
Output
capacitances. When these transients
flow through the parasitic
inductance between the device
ground pin and the test system ground,
significant reductions in observable
noise immunity can result. Numbers
250 Ω
(8.06 kΩ)
[481 Ω]
without parentheses are for 5.0-V
Device input
devices or outputs. Numbers in
rise and fall
parentheses are for 3.3-V devices or times < 3 ns
outputs. Numbers in brackets are for
2.5-V devices or outputs.
VCC
To Test
System
C1 (includes
JIG capacitance)
30
Altera Corporation