EPF6016ATI144-3N Datasheet, PDF (14/52 Pages) Altera Corporation – Programmable Logic Device Family

FLEX 6000 Programmable Logic Device Family Data Sheet
Figure 7. LE Operating Modes
Normal Mode
Carry-In
data1
data2
data3
data4
Cascade-In
4-Input
LUT
Cascade-Out
PRN
DQ
CLRN
LE-Out
Arithmetic Mode
Carry-In
Cascade-In
data1
data2
3-Input
LUT
3-Input
LUT
Carry-Out
PRN
DQ
CLRN
Cascade-Out
LE-Out
Counter Mode
Carry-In
(1)
Cascade-In
LAB-Wide
Synchronous
Load (3)
LAB-Wide Synchronous
Clear (3)
data1 (2)
data2 (2)
data3 (data)
3-Input
LUT
3-Input
LUT
Carry-Out Cascade-Out
PRN
DQ
CLRN
LE-Out
Notes:
(1) The register feedback multiplexer is available on LE 2 of each LAB.
(2) The data1 and data2 input signals can supply a clock enable, up or down control, or register feedback signals for
all LEs other than the second LE in an LAB.
(3) The LAB-wide synchronous clear and LAB-wide synchronous load affect all registers in an LAB.
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Altera Corporation