EPF6016ATI144-3N Datasheet, PDF (26/52 Pages) Altera Corporation – Programmable Logic Device Family

FLEX 6000 Programmable Logic Device Family Data Sheet
Figure 15. SameFrame Pin-Out Example
Printed Circuit Board
Designed for 256-Pin FineLine BGA Package
100-Pin
FineLine
BGA
256-Pin
FineLine
BGA
Output
Configuration
26
100-Pin FineLine BGA Package
(Reduced I/O Count or
Logic Requirements)
256-Pin FineLine BGA Package
(Increased I/O Count or
Logic Requirements)
Table 6 lists the 3.3-V FLEX 6000 devices with the SameFrame pin-out
feature.
Table 6. 3.3-V FLEX 6000 Devices with SameFrame Pin-Outs
Device
EPF6016A
EPF6024A
100-Pin FineLine BGA
v
256-Pin FineLine BGA
v
v
This section discusses slew-rate control, the MultiVolt I/O interface,
power sequencing, and hot-socketing for FLEX 6000 devices.
Slew-Rate Control
The output buffer in each IOE has an adjustable output slew-rate that can
be configured for low-noise or high-speed performance. A slower
slew-rate reduces system noise and adds a maximum delay of 6.8 ns. The
fast slew-rate should be used for speed-critical outputs in systems that are
adequately protected against noise. Designers can specify the slew-rate on
a pin-by-pin basis during design entry or assign a default slew rate to all
pins on a device-wide basis. The slew-rate setting affects only the falling
edge of the output.
Altera Corporation