MT47H64M8B6-25ELDTR Datasheet, PDF (8/133 Pages) Micron Technology – 512Mb: x4, x8, x16 DDR2 SDRAM

512Mb: x4, x8, x16 DDR2 SDRAM
Features
List of Tables
Table 1: Key Timing Parameters ....................................................................................................................... 2
Table 2: Addressing ......................................................................................................................................... 2
Table 3: FBGA 84-Ball – x16 and 60-Ball – x4, x8 Descriptions .......................................................................... 16
Table 4: Input Capacitance ............................................................................................................................ 20
Table 5: Absolute Maximum DC Ratings ......................................................................................................... 21
Table 6: Temperature Limits .......................................................................................................................... 22
Table 7: Thermal Impedance ......................................................................................................................... 22
Table 8: General I_DD Parameters ..................................................................................................................... 24
Table 9: I_DD7 Timing Patterns (4-Bank Interleave READ Operation) ................................................................. 24
Table 10: DDR2 I_DD Specifications and Conditions (Die Revision F) ................................................................. 25
Table 11: DDR2 I_DD Specifications and Conditions (Die Revision G) ................................................................ 28
Table 12: AC Operating Specifications and Conditions .................................................................................... 31
Table 13: Recommended DC Operating Conditions (SSTL_18) ........................................................................ 43
Table 14: ODT DC Electrical Characteristics ................................................................................................... 44
Table 15: Input DC Logic Levels ..................................................................................................................... 45
Table 16: Input AC Logic Levels ...................................................................................................................... 45
Table 17: Differential Input Logic Levels ......................................................................................................... 46
Table 18: Differential AC Output Parameters ................................................................................................... 48
Table 19: Output DC Current Drive ................................................................................................................ 48
Table 20: Output Characteristics .................................................................................................................... 49
Table 21: Full Strength Pull-Down Current (mA) ............................................................................................. 50
Table 22: Full Strength Pull-Up Current (mA) .................................................................................................. 51
Table 23: Reduced Strength Pull-Down Current (mA) ...................................................................................... 52
Table 24: Reduced Strength Pull-Up Current (mA) .......................................................................................... 53
Table 25: Input Clamp Characteristics ............................................................................................................ 54
Table 26: Address and Control Balls ................................................................................................................ 55
Table 27: Clock, Data, Strobe, and Mask Balls ................................................................................................. 55
Table 28: AC Input Test Conditions ................................................................................................................ 55
Table 29: DDR2-400/533 Setup and Hold Time Derating Values (^tIS and ^tIH) .................................................... 58
Table 30: DDR2-667/800/1066 Setup and Hold Time Derating Values (^tIS and ^tIH) ........................................... 59
Table 31: DDR2-400/533 ^tDS, ^tDH Derating Values with Differential Strobe ...................................................... 62
Table 32: DDR2-667/800/1066 ^tDS, ^tDH Derating Values with Differential Strobe ............................................. 63
Table 33: Single-Ended DQS Slew Rate Derating Values Using ^tDS_b and ^tDH_b ................................................... 64
Table 34: Single-Ended DQS Slew Rate Fully Derated (DQS, DQ at V_REF) at DDR2-667 ...................................... 64
Table 35: Single-Ended DQS Slew Rate Fully Derated (DQS, DQ at V_REF) at DDR2-533 ...................................... 65
Table 36: Single-Ended DQS Slew Rate Fully Derated (DQS, DQ at V_REF) at DDR2-400 ...................................... 65
Table 37: Truth Table – DDR2 Commands ...................................................................................................... 70
Table 38: Truth Table – Current State Bank n – Command to Bank n ................................................................ 71
Table 39: Truth Table – Current State Bank n – Command to Bank m ............................................................... 73
Table 40: Minimum Delay with Auto Precharge Enabled ................................................................................. 74
Table 41: Burst Definition .............................................................................................................................. 78
Table 42: READ Using Concurrent Auto Precharge .......................................................................................... 98
Table 43: WRITE Using Concurrent Auto Precharge ....................................................................................... 104
Table 44: Truth Table – CKE .......................................................................................................................... 119
PDF: 09005aef82f1e6e2
512MbDDR2.pdf - Rev. T 2/12 EN
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