MT47H64M8B6-25ELDTR Datasheet, PDF (121/133 Pages) Micron Technology – 512Mb: x4, x8, x16 DDR2 SDRAM

512Mb: x4, x8, x16 DDR2 SDRAM
Power-Down Mode
Figure 71: WRITE-to-Power-Down or Self Refresh Entry
CK#
CK
Command
T0
WRITE
CKE
Address
A10
DQS, DQS#
Valid
DQ
T1
T2
NOP
NOP
T3
T4
NOP
Valid
T5
Valid
T6
Valid
T7
NOP1
T8
tCKE _(MIN)
WL = 3
DO DO DO DO
tWTR
Power-down or
self refresh entry1
Transitioning Data
Don’t Care
Note: 1. Power-down or self refresh entry may occur after the WRITE burst completes.
Figure 72: WRITE with Auto Precharge-to-Power-Down or Self Refresh Entry
T0
T1
T2
T3
T4
T5
Ta0
Ta1
Ta2
CK#
CK
Command WRITE
NOP
NOP
NOP
Valid
Valid
Valid1
NOP
tCKE _(MIN)
CKE
Address Valid
A10
DQS, DQS#
DQ
WL = 3
DO DO DO DO
WR2
Indicates a break in
time scale
Power-down or
self refresh entry
Transitioning Data
Don’t Care
Notes:
1. Internal PRECHARGE occurs at Ta0 when WR has completed; power-down entry may oc-
cur 1 x ^tCK later at Ta1, prior to ^tRP being satisfied.
2. WR is programmed through MR9–MR11 and represents (^tWR [MIN] ns/^tCK) rounded up
to next integer ^tCK.
PDF: 09005aef82f1e6e2
512MbDDR2.pdf - Rev. T 2/12 EN
121
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