MT47H64M8B6-25ELDTR Datasheet, PDF (108/133 Pages) Micron Technology – 512Mb: x4, x8, x16 DDR2 SDRAM

512Mb: x4, x8, x16 DDR2 SDRAM
WRITE
Figure 60: WRITE-to-READ
T0
T1
CK#
CK
Command
WRITE
NOP
T2 T2n T3 T3n T4
NOP
NOP
NOP
Address
Bank a,
Col b
tDQSS _(NOM)
DQS, DQS#
WL ± ^tDQSS
DQ
DI
b
DM
tDQSS _(MIN)
DQS, DQS#
DQ
DM
WL - ^tDQSS
DI
b
tDQSS _(MAX)
DQS, DQS#
DQ
DM
WL + ^tDQSS
DI
b
2
2
2
T5
NOP
tWTR1
T6
T7
READ
Bank a,
Col n
NOP
CL = 3
CL = 3
CL = 3
T8
NOP
T9 T9n
NOP
DI
DI
DI
Transitioning Data
Don’t Care
Notes:
1. ^tWTR is required for any READ following a WRITE to the same device, but it is not re-
quired between module ranks.
2. Subsequent rising DQS signals must align to the clock within ^tDQSS.
3. DI b = data-in for column b; DO n = data-out from column n.
4. BL = 4, AL = 0, CL = 3; thus, WL = 2.
5. One subsequent element of data-in is applied in the programmed order following DI b.
6. ^tWTR is referenced from the first positive CK edge after the last data-in pair.
7. A10 is LOW with the WRITE command (auto precharge is disabled).
8. The number of clock cycles required to meet ^tWTR is either 2 or ^tWTR/^tCK, whichever is
greater.
PDF: 09005aef82f1e6e2
512MbDDR2.pdf - Rev. T 2/12 EN
108
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