MT47H64M8B6-25ELDTR Datasheet, PDF (6/133 Pages) Micron Technology – 512Mb: x4, x8, x16 DDR2 SDRAM

512Mb: x4, x8, x16 DDR2 SDRAM
Features
List of Figures
Figure 1: 512Mb DDR2 Part Numbers ............................................................................................................... 2
Figure 2: Simplified State Diagram ................................................................................................................... 9
Figure 3: 128 Meg x 4 Functional Block Diagram ............................................................................................. 12
Figure 4: 64 Meg x 8 Functional Block Diagram ............................................................................................... 13
Figure 5: 32 Meg x 16 Functional Block Diagram ............................................................................................. 13
Figure 6: 60-Ball FBGA – x4, x8 Ball Assignments (Top View) ........................................................................... 14
Figure 7: 84-Ball FBGA – x16 Ball Assignments (Top View) ............................................................................... 15
Figure 8: 84-Ball FBGA (8mm x 12.5mm) – x16 ................................................................................................ 18
Figure 9: 60-Ball FBGA (8mm x 10mm) – x4, x8 ............................................................................................... 19
Figure 10: Example Temperature Test Point Location ...................................................................................... 22
Figure 11: Single-Ended Input Signal Levels ................................................................................................... 45
Figure 12: Differential Input Signal Levels ...................................................................................................... 46
Figure 13: Differential Output Signal Levels .................................................................................................... 48
Figure 14: Output Slew Rate Load .................................................................................................................. 49
Figure 15: Full Strength Pull-Down Characteristics ......................................................................................... 50
Figure 16: Full Strength Pull-Up Characteristics .............................................................................................. 51
Figure 17: Reduced Strength Pull-Down Characteristics .................................................................................. 52
Figure 18: Reduced Strength Pull-Up Characteristics ...................................................................................... 53
Figure 19: Input Clamp Characteristics .......................................................................................................... 54
Figure 20: Overshoot ..................................................................................................................................... 55
Figure 21: Undershoot ................................................................................................................................... 55
Figure 22: Nominal Slew Rate for ^tIS ............................................................................................................... 60
Figure 23: Tangent Line for ^tIS ........................................................................................................................ 60
Figure 24: Nominal Slew Rate for ^tIH .............................................................................................................. 61
Figure 25: Tangent Line for ^tIH ....................................................................................................................... 61
Figure 26: Nominal Slew Rate for ^tDS ............................................................................................................. 66
Figure 27: Tangent Line for ^tDS ...................................................................................................................... 66
Figure 28: Nominal Slew Rate for ^tDH ............................................................................................................. 67
Figure 29: Tangent Line for ^tDH ..................................................................................................................... 67
Figure 30: AC Input Test Signal Waveform Command/Address Balls ................................................................ 68
Figure 31: AC Input Test Signal Waveform for Data with DQS, DQS# (Differential) ............................................ 68
Figure 32: AC Input Test Signal Waveform for Data with DQS (Single-Ended) ................................................... 69
Figure 33: AC Input Test Signal Waveform (Differential) .................................................................................. 69
Figure 34: MR Definition ............................................................................................................................... 77
Figure 35: CL ................................................................................................................................................. 80
Figure 36: EMR Definition ............................................................................................................................. 81
Figure 37: READ Latency ............................................................................................................................... 84
Figure 38: WRITE Latency .............................................................................................................................. 84
Figure 39: EMR2 Definition ........................................................................................................................... 85
Figure 40: EMR3 Definition ........................................................................................................................... 86
Figure 41: DDR2 Power-Up and Initialization ................................................................................................. 87
Figure 42: Example: Meeting ^tRRD (MIN) and ^tRCD (MIN) .............................................................................. 90
Figure 43: Multibank Activate Restriction ....................................................................................................... 91
Figure 44: READ Latency ............................................................................................................................... 93
Figure 45: Consecutive READ Bursts .............................................................................................................. 94
Figure 46: Nonconsecutive READ Bursts ........................................................................................................ 95
Figure 47: READ Interrupted by READ ............................................................................................................ 96
Figure 48: READ-to-WRITE ............................................................................................................................ 96
Figure 49: READ-to-PRECHARGE – BL = 4 ...................................................................................................... 97
Figure 50: READ-to-PRECHARGE – BL = 8 ...................................................................................................... 97
PDF: 09005aef82f1e6e2
512MbDDR2.pdf - Rev. T 2/12 EN
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