MT47H64M8B6-25ELDTR Datasheet, PDF (28/133 Pages) Micron Technology – 512Mb: x4, x8, x16 DDR2 SDRAM

512Mb: x4, x8, x16 DDR2 SDRAM
Electrical Specifications – I_DD Parameters
Table 11: DDR2 I_DD Specifications and Conditions (Die Revision G)
Notes: 1–7 apply to the entire table
Configura-
-25E/
Parameter/Condition
Symbol
tion
-187E -25 -3E/-3 -37E -5E
Operating one bank active-pre-
I_DD0
charge current: ^tCK = ^tCK (I_DD), ^tRC =
t_{RC (IDD),} t_{RAS =} t_{RAS MIN (IDD); CKE is}
HIGH, CS# is HIGH between valid com-
mands; address bus inputs are switch-
ing; Data bus inputs are switching
x4, x8
x16
75
65
60
55
55
90
80
75
70
70
Operating one bank active-read-
I_DD1
precharge current: I_OUT = 0mA; BL =
4, CL = CL (I_DD), AL = 0; ^tCK = ^tCK (I_DD),
t_{RC =} t_{RC (IDD),} t_{RAS =} t_{RAS MIN (IDD),}
t_{RCD =} t_{RCD (IDD); CKE is HIGH, CS# is}
HIGH between valid commands; ad-
x4, x8
x16
85
75
100
95
dress bus inputs are switching; Data
pattern is same as I_DD4W
Precharge power-down current:
I_DD2P x4, x8, x16
7
7
All banks idle; ^tCK = ^tCK (I_DD); CKE is
LOW; Other control and address bus
inputs are stable; Data bus inputs are
floating
70
65
65
90
85
85
7
7
7
Precharge quiet standby current:
All banks idle; ^tCK = ^tCK (I_DD); CKE is
HIGH, CS# is HIGH; Other control and
address bus inputs are stable; Data
bus inputs are floating
I_DD2Q
x4, x8
x16
28
24
22
20
19
30
26
24
22
20
Precharge standby current: All
banks idle; ^tCK = ^tCK (I_DD); CKE is
HIGH, CS# is HIGH; Other control and
address bus inputs are switching; Da-
ta bus inputs are switching
I_DD2N
x4, x8
x16
34
28
25
23
21
36
30
27
25
23
Active power-down current: All
I_DD3Pf Fast PDN exit 23
18
15
14
13
banks open; ^tCK = ^tCK (I_DD); CKE is
MR12 = 0
LOW; Other control and address bus _{IDD3Ps Slow PDN exit 9}
9
9
9
9
inputs are stable; Data bus inputs are
MR12 = 1
floating
Active standby current: All banks
open; ^tCK = ^tCK (I_DD), ^tRAS = ^tRAS
MAX (I_DD), ^tRP = ^tRP (I_DD); CKE is
HIGH, CS# is HIGH between valid com-
mands; Other control and address bus
inputs are switching; Data bus inputs
are switching
I_DD3N
x4, x8
x16
40
33
30
27
24
42
35
32
29
26
Units
mA
mA
mA
mA
mA
mA
mA
PDF: 09005aef82f1e6e2
512MbDDR2.pdf - Rev. T 2/12 EN
28
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