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EP2AGX125EF29I5N Datasheet, PDF (8/78 Pages) Altera Corporation – Device Datasheet for Arria II Devices | |||
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1â8
Chapter 1: Device Datasheet for Arria II Devices
Electrical Characteristics
I/O Pin Leakage Current
Table 1â7 lists the Arria II GX I/O pin leakage current specifications.
Table 1â7. I/O Pin Leakage Current for Arria II GX Devices
Symbol
II
IOZ
Description
Input pin
Tri-stated I/O pin
Conditions
VI = 0 V to VCCIOMAX
VO = 0 V to VCCIOMAX
Min
Typ
Max Unit
â10
â
10
µA
â10
â
10
µA
Table 1â8 lists the Arria II GZ I/O pin leakage current specifications.
Table 1â8. I/O Pin Leakage Current for Arria II GZ Devices
Symbol
II
IOZ
Description
Input pin
Tri-stated I/O pin
Conditions
VI = 0 V to VCCIOMAX
VO = 0 V to VCCIOMAX
Min
Typ
Max Unit
â20
â
20
µA
â20
â
20
µA
Bus Hold
Bus hold retains the last valid logic state after the source driving it either enters the
high impedance state or is removed. Each I/O pin has an option to enable bus hold in
user mode. Bus hold is always disabled in configuration mode.
Table 1â9 lists bus hold specifications for Arria II GX devices.
Table 1â9. Bus Hold Parameters for Arria II GX Devices (Note 1)
VCCIO (V)
Parameter Symbol Cond.
1.2
1.5
1.8
2.5
3.0
3.3
Unit
Min Max Min Max Min Max Min Max Min Max Min Max
Bus-hold
low,
sustaining
ISUSL
VIN > VIL
(max.)
8
â
12
â
30
â
50
â 70 â 70 â µA
current
Bus-hold
high,
sustaining
ISUSH
VIN < VIL
(min.)
â8
â
â12
â
â30
â
â50
â â70 â â70 â µA
current
Bus-hold
low,
overdrive
current
IODL
0 V < VIN <
VCCIO
â
125
â
175
â
200
â
300 â 500 â 500 µA
Bus-hold
high,
overdrive
current
IODH
0 V < VIN <
VCCIO
â
â125
â
â175
â
â200
â
â300 â â500 â â500 µA
Bus-hold
trip point
VTRIP
â
0.3 0.9 0.375 1.125 0.68 1.07 0.7 1.7 0.8 2 0.8 2 V
Note to Table 1â9:
(1) The bus-hold trip points are based on calculated input voltages from the JEDEC standard.
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
July 2012 Altera Corporation
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