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EP2AGX125EF29I5N Datasheet, PDF (28/78 Pages) Altera Corporation – Device Datasheet for Arria II Devices | |||
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1â28
Chapter 1: Device Datasheet for Arria II Devices
Switching Characteristics
Table 1â35 lists the transceiver specifications for Arria II GZ devices.
Table 1â35. Transceiver Specifications for Arria II GZ Devices (Part 1 of 5)
Symbol/
Description
Conditions
âC3 and âI3 (1)
Min Typ
Max
âC4 and âI4
Unit
Min Typ
Max
Reference Clock
Supported I/O Standards
Input frequency from
REFCLK input pins
Phase frequency detector
(CMU PLL and receiver
CDR)
Absolute VMAX for a REFCLK
pin
Operational VMAX for a
REFCLK pin
Absolute VMIN for a REFCLK
pin
Rise/fall time (2)
Duty cycle
Peak-to-peak differential
input voltage
Spread-spectrum
modulating clock frequency
Spread-spectrum
downspread
On-chip termination
resistors
VICM (AC coupled)
VICM (DC coupled)
Transmitter REFCLK Phase
Noise
Transmitter REFCLK Phase
Jitter (rms) for 100 MHz
REFCLK (3)
RREF
1.2-V PCML, 1.5-V PCML, 2.5-V PCML, Differential LVPECL, LVDS, and HCSL
â
50
â
697
50
â
637.5 MHz
â
50
â
325
50
â
325 MHz
â
â
â
1.6
â
â
â
1.5
â
-0.4
â
â
â
â
â
0.2
â
45
â
55
â
200
â
1600
PCIe
PCIe
â
â
HCSL I/O standard
for PCIe reference
clock
10 Hz
100 Hz
1 KHz
10 KHz
100 KHz
ï³ 1 MHz
30
â
33
0 to
â
â
-0.5%
â
100
â
1100 ± 10%
250
â
550
â
â
-50
â
â
-80
â
â
-110
â
â
-120
â
â
-120
â
â
-130
10 KHz to 20 MHz â
â
3
â
â
2000 ±
1%
â
â
â
1.6
V
â
â
1.5
V
-0.4 â
â
V
â
â
0.2
UI
45
â
55
%
200
â
1600 mV
30
â
33
kHz
0 to
â
â
â
-0.5%
â
100
â
ï
1100 ± 10%
mV
250
â
550
mV
â
â
-50 dBc/Hz
â
â
-80 dBc/Hz
â
â
-110 dBc/Hz
â
â
-120 dBc/Hz
â
â
-120 dBc/Hz
â
â
-130 dBc/Hz
â
â
3
ps
â
2000 ±
1%
â
ï
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
July 2012 Altera Corporation
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