EP2AGX125EF29I5N Datasheet, PDF (27/78 Pages) Altera Corporation – Device Datasheet for Arria II Devices

Table 1–34. Transceiver Specifications for Arria II GX Devices (Note 1) (Part 7 of 7)
Symbol/
Description
Condition
Min
I3
C4
C5 and I5
C6
Unit
Typ
Max Min Typ
Max
Min
Typ
Max Min Typ Max
Digital reset
pulse width
—
Minimum is 2 parallel clock cycles
Notes to Table 1–34:
(1) For AC-coupled links, the on-chip biasing circuit is switched off before and during configuration. Ensure that input specifications are not violated during this period.
(2) The rise/fall time is specified from 20% to 80%.
(3) To calculate the REFCLK rms phase jitter requirement at reference clock frequencies other than 100 MHz, use the following formula:
REFCLK rms phase jitter at f (MHz) = REFCLK rms phase jitter at 100 MHz * 100/f.
(4) The minimum reconfig_clk frequency is 2.5 MHz if the transceiver channel is configured in Transmitter only mode. The minimum reconfig_clk frequency is 37.5 MHz if the transceiver channel is
configured in Receiver only or Receiver and Transmitter mode. For more information, refer to AN 558: Implementing Dynamic Reconfiguration in Arria II Devices.
(5) If your design uses more than one dynamic reconfiguration controller instances (altgx_reconfig) to control the transceiver channels (altgx) physically located on the same side of the device, and if
you use different reconfig_clk sources for these altgx_reconfig instances, the delta time between any two of these reconfig_clk sources becoming stable must not exceed the maximum
specification listed.
(6) The device cannot tolerate prolonged operation at this absolute maximum.
(7) You must use the 1.1-V RX V_ICM setting if the input serial data standard is LVDS and the link is DC-coupled.
(8) The rate matcher supports only up to ±300 parts per million (ppm).
(9) Time taken to rx_pll_locked goes high from rx_analogreset de-assertion. Refer to Figure 1–1.
(10) The time in which the CDR must be kept in lock-to-reference mode after rx_pll_locked goes high and before rx_locktodata is asserted in manual mode. Refer to Figure 1–1.
(11) The time taken to recover valid data after the rx_locktodata signal is asserted in manual mode. Refer to Figure 1–1.
(12) The time taken to recover valid data after the rx_freqlocked signal goes high in automatic mode. Refer to Figure 1–2.