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EP2AGX125EF29I5N Datasheet, PDF (30/78 Pages) Altera Corporation – Device Datasheet for Arria II Devices | |||
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1â30
Chapter 1: Device Datasheet for Arria II Devices
Switching Characteristics
Table 1â35. Transceiver Specifications for Arria II GZ Devices (Part 3 of 5)
Symbol/
Description
Receiver DC Coupling
Support
Differential on-chip
termination resistors
Differential and common
mode return loss
Programmable PPM
detector (9)
Run length
Programmable equalization
tLTR (10)
tLTR_LTD_Manual (11)
tLTD_Manual (12)
tLTD_Auto (13)
Receiver CDR
3 dB Bandwidth in
lock-to-data (LTD) mode
Conditions
â
85ïï setting
100ïï setting
120ïï setting
150-ï setting
PCIe (Gen 1 and
Gen 2),
XAUI,
HiGig+,
CEI SR/LR,
SRIO SR/LR,
CPRI LV/HV,
OBSAI,
SATA
âC3 and âI3 (1)
Min Typ
Max
âC4 and âI4
Unit
Min Typ
Max
For more information about receiver DC coupling support, refer to the
âDC-Coupled Linksâ section in the Transceiver Architecture for Arria II
Devices chapter.
85 ± 20%
85 ± 20%
ï
100 ± 20%
100 ± 20%
ï
120 ± 20%
120 ± 20%
ï
150 ± 20%
150 ± 20%
ï
Compliant
â
â
± 62.5, 100, 125, 200, 250, 300, 500, 1,000
ppm
â
â
â
200
â
â
200
UI
â
â
â
16
â
â
16
dB
â
â
â
75
â
â
75
µs
â
15
â
â
15
â
â
µs
â
â
â
4000
â
â
4000
ns
â
â
â
4000
â
â
4000
ns
PCIe Gen1
2.0 - 3.5
MHz
PCIe Gen2
40 - 65
MHz
(OIF) CEI PHY at
6.375 Gbps
20 - 35
MHz
XAUI
10 - 18
MHz
SRIO 1.25 Gbps
10 - 18
MHz
SRIO 2.5 Gbps
10 - 18
MHz
SRIO 3.125 Gbps
6 - 10
MHz
GIGE
6 - 10
MHz
SONET OC12
3-6
MHz
SONET OC48
14 - 19
MHz
Receiver buffer and CDR
offset cancellation time (per
â
â
channel)
Programmable DC gain
DC Gain Setting = 0 â
DC Gain Setting = 1 â
DC Gain Setting = 2 â
â
17000
â
0
â
â
3
â
â
6
â
â
recon
â
17000 fig_
clk
cycles
0
â
dB
3
â
dB
6
â
dB
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
July 2012 Altera Corporation
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