EP2AGX125EF29I5N Datasheet, PDF (31/78 Pages) Altera Corporation – Device Datasheet for Arria II Devices

Chapter 1: Device Datasheet for Arria II Devices
Switching Characteristics
1–31
Table 1–35. Transceiver Specifications for Arria II GZ Devices (Part 4 of 5)
Symbol/
Description
Conditions
–C3 and –I3 (1)
Min Typ
Max
–C4 and –I4
Min Typ
Max
Transmitter
Supported I/O Standards
Data rate (14)
V_OCM
Differential on-chip
termination resistors
Differential and common
mode return loss
Rise time (15)
Fall time (15)
Intra-differential pair skew
Intra-transceiver block
transmitter
channel-to-channel skew
Inter-transceiver block
transmitter
channel-to-channel skew
—
0.65 V setting
85 setting
100 setting
120 setting
150- setting
PCIe Gen1 and
Gen2 (TX V_OD=4),
XAUI (TX V_OD=6),
HiGig+
(TX V_OD=6),
CEI SR/LR
(TX V_OD=8),
SRIO SR (V_OD=6),
SRIO LR (V_OD=8),
CPRI LV (V_OD=6),
CPRI HV (V_OD=2),
OBSAI (V_OD=6),
SATA (V_OD=4),
—
—
—
×4 PMA and PCS
bonded mode
Example: XAUI,
PCIe ×4, Basic ×4
×8 PMA and PCS
bonded mode
Example: PCIe ×8,
Basic ×8
1.5-V PCML
600
—
6375 600 —
3750
—
650
—
—
650
—
85 ± 15%
85 ± 15%
100 ± 15%
100 ± 15%
120 ± 15%
120 ± 15%
150 ± 15%
150 ± 15%
Compliant
50
—
200
50
—
200
50
—
200
50
—
200
—
—
15
—
—
15
—
—
120
—
—
120
—
—
500
—
—
500
CMU0 PLL and CMU1 PLL
Supported Data Range
—
pll_powerdown minimum
pulse width
—
(tpll_powerdown)
CMU PLL lock time from
pll_powerdown
—
de-assertion
600
—
6375
600
—
3750
1
1
—
—
100
—
—
100
Unit
Mbps
mV




—
ps
ps
ps
ps
ps
Mbps
s
s
July 2012 Altera Corporation
Arria II Device Handbook Volume 3: Device Datasheet and Addendum