EP2AGX260FF35I3N Datasheet, PDF (75/78 Pages) Altera Corporation – Device Datasheet for Arria II Devices

Chapter 1: Device Datasheet for Arria II Devices
Glossary
1–75
Table 1–68. Glossary (Part 2 of 4)
Letter Subject
Definitions
J
High-speed I/O block: Deserialization factor (width of parallel data bus).
JTAG Timing Specifications:
G,
H,
I,
JTAG Timing
Specifications
J
TMS
TDI
TCK
TDO
t _JCP
t _JCH
t _JCL
t_JPZX
t _JPSU
t_JPCO
t _JPH
t _JPXZ
PLL Specification parameters:
Diagram of PLL Specifications (1)
K,
L,
M, _PLL
N, ^{Specifications}
O,
P
CLK
Core Clock
Switchover
CLKOUT Pins
fOUT_EXT
fIN
fINPFD
N
PFD CP
LF VCO K ^{fVCO /K}
(2)
Counters
C0..C9
fOUT
GCLK
Key
Reconfigurable in User Mode
M
External Feedback
RCLK
Q,
R ^RL
Notes:
(1) CoreClock can only be fed by dedicated clock input pins or PLL outputs.
(2) This is the VCO post-scale counter K.
Receiver differential input discrete resistor (external to the Arria II device).
July 2012 Altera Corporation
Arria II Device Handbook Volume 3: Device Datasheet and Addendum