EP2AGX260FF35I3N Datasheet, PDF (56/78 Pages) Altera Corporation – Device Datasheet for Arria II Devices

1–56
Chapter 1: Device Datasheet for Arria II Devices
Switching Characteristics
Table 1–45. PLL Specifications for Arria II GZ Devices (Part 2 of 2)
Symbol
Parameter
Min Typ
Max
Unit
t_DLOCK
Time required to lock dynamically (after switchover or
reconfiguring any non-post-scale counters/delays)
—
—
1
ms
PLL closed-loop low bandwidth
— 0.3
—
MHz
f_CLBW
PLL closed-loop medium bandwidth
PLL closed-loop high bandwidth (7)
— 1.5
—
MHz
—
4
—
MHz
t_{PLL_PSERR}
Accuracy of PLL phase shift
—
—
t_ARESET
Minimum pulse width on the areset signal
10
—
t_INCCJ (3), (4)
Input clock cycle to cycle jitter (F_REF ≥ 100 MHz)
Input clock cycle to cycle jitter (F_REF < 100 MHz)
—
—
—
—
t_{OUTPJ_DC} (5)
Period Jitter for dedicated clock output (F_OUT ≥ 100 MHz)
Period Jitter for dedicated clock output (F_OUT < 100 MHz)
—
—
—
—
t_{OUTCCJ_DC} (5)
Cycle to Cycle Jitter for dedicated clock output
(F_OUT ≥ 100 MHz)
Cycle to Cycle Jitter for dedicated clock output
(F_OUT < 100 MHz)
—
—
—
—
t_{OUTPJ_IO} (5),
(8)
Period Jitter for clock output on regular I/O
(F_OUT ≥ 100 MHz)
Period Jitter for clock output on regular I/O
(F_OUT < 100 MHz)
—
—
—
—
t_{OUTCCJ_IO} (5),
(8)
Cycle to Cycle Jitter for clock output on regular I/O
(F_OUT ≥ 100 MHz)
Cycle to Cycle Jitter for clock output on regular I/O
(F_OUT < 100 MHz)
—
—
—
—
Period Jitter for dedicated clock output in cascaded PLLs
t_{CASC_OUTPJ_DC} ^(FOUT ^{≥100MHz)}
—
—
(5), (6)
Period Jitter for dedicated clock output in cascaded PLLs
(F_OUT < 100MHz)
—
—
f_DRIFT
Frequency drift after PFDENA is disabled for duration of
100 us
—
—
±50
—
0.15
±750
175
17.5
175
17.5
600
60
600
60
250
25
±10
ps
ns
UI (p-p)
ps (p-p)
ps (p-p)
mUI (p-p)
ps (p-p)
mUI (p-p)
ps (p-p)
mUI (p-p)
ps (p-p)
mUI (p-p)
ps (p-p)
mUI (p-p)
%
Notes to Table 1–45:
(1) This specification is limited in the Quartus II software by the I/O maximum frequency. The maximum I/O frequency is different for each I/O
standard.
(2) This specification is limited by the lower of the two: I/O F_MAX or F_OUT of the PLL.
(3) A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source that is less
than 120 ps.
(4) F_REF is fIN/N when N = 1.
(5) Peak-to-peak jitter with a probability level of 10^–12 (14 sigma, 99.99999999974404% confidence level). The output jitter specification applies
to the intrinsic jitter of the PLL, when an input jitter of 30 ps is applied. The external memory interface clock output jitter specifications use a
different measurement method and are available in Table 1–64 on page 1–71.
(6) The cascaded PLL specification is only applicable with the following condition:
a. Upstream PLL: 0.59 Mhz  Upstream PLL BW < 1 MHz
b. Downstream PLL: Downstream PLL BW > 2 MHz
(7) High bandwidth PLL settings are not supported in external feedback mode.
(8) External memory interface clock output jitter specifications use a different measurement method, which is available in Table 1–63 on
page 1–71.
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
July 2012 Altera Corporation