EP2AGX260FF35I3N Datasheet, PDF (64/78 Pages) Altera Corporation – Device Datasheet for Arria II Devices

1–64
Chapter 1: Device Datasheet for Arria II Devices
Switching Characteristics
Table 1–53. High-Speed I/O Specifications for Arria II GX Devices (Part 4 of 4)
Symbol
Conditions
I3
Min Max
C4
Min Max
C5,I5
C6
Unit
Min Max Min Max
SERDES factor
J = 3 to 10
(3)
945
(7)
(3)
945
(7)
(3)
740
(7)
(3)
640
(7)
Mbps
SERDES factor
f_HSDR (data rate)
J = 2 (using
DDR registers)
(3)
(7)
(3)
(7)
(3)
(7)
(3)
(7) Mbps
SERDES factor
J = 1 (using (3) (7)
(3)
(7)
(3)
(7)
(3)
(7) Mbps
SDR registers)
Soft-CDR PPM
tolerance
Soft-CDR
mode
— 300
—
300
—
300 — 300 PPM
DPA run length
DPA mode
— 10,000 — 10,000 — 10,000 — 10,000 UI
Sampling
window (SW)
Non-DPA mode
(5)
—
300
—
300
—
350 — 400 ps
Notes to Table 1–53:
(1) f_{HSCLK_IN} = f_HSDR / W. Use W to determine the supported selection of input reference clock frequencies for the desired data rate.
(2) Applicable for interfacing with DPA receivers only. For interfacing with non-DPA receivers, you must calculate the leftover timing margin in the
receiver by performing link timing closure analysis. For Arria II GX transmitter to Arria II GX non-DPA receiver, the maximum supported data
rate is 945 Mbps. For data rates above 840 Mbps, perform PCB trace compensation by adjusting the PCB trace length for LVDS channels to
improve channel-to-channel skews.
(3) The minimum and maximum specification depends on the clock source (for example, PLL and clock pin) and the clock routing resource you
use (global, regional, or local). The I/O differential buffer and input register do not have a minimum toggle rate.
(4) The specification is only applicable under the influence of core noise.
(5) Applicable for true LVDS using dedicated SERDES only.
(6) Dedicated SERDES and DPA features are only available on the right banks.
(7) You must calculate the leftover timing margin in the receiver by performing link timing closure analysis. You must consider the board skew
margin, transmitter channel-to-channel skew, and the receiver sampling margin to determine the leftover timing margin.
Table 1–54 lists the high-speed I/O timing for Arria II GZ devices.
Table 1–54. High-Speed I/O Specifications for Arria II GZ Devices (Note 1), (2), (10) (Part 1 of 3)
Symbol
Conditions
C3, I3
C4, I4
Unit
Min
Typ
Max
Min
Typ
Max
Clock
f_{HSCLK_in} (input clock
frequency) true
differential I/O
Clock boost factor
W = 1 to 40 (3)
5
—
717
standards
f_{HSCLK_in} (input clock
frequency) single
ended I/O standards
Clock boost factor
W = 1 to 40 (3)
5
—
717
(9)
f_{HSCLK_in} (input clock
frequency) single
ended I/O standards
Clock boost factor
W = 1 to 40 (3)
5
—
420
(10)
5
—
717
MHz
5
—
717
MHz
5
—
420
MHz
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
July 2012 Altera Corporation