EP2AGX260FF35I3N Datasheet, PDF (74/78 Pages) Altera Corporation – Device Datasheet for Arria II Devices

1–74
Chapter 1: Device Datasheet for Arria II Devices
Glossary
Glossary
Table 1–68 lists the glossary for this chapter.
Table 1–68. Glossary (Part 1 of 4)
Letter
Subject
Receiver Input Waveforms
Definitions
Single-Ended Waveform
V_ID
V_CM
Positive Channel (p) = V_IH
Negative Channel (n) = V_IL
Ground
Differential Waveform
V_ID
A,
B, _{Differential I/O}
C, ^Standards
D
Transmitter Output Waveforms
Single-Ended Waveform
V_CM
V_OD
p−n=0V
V_ID
Positive Channel (p) = V_OH
Negative Channel (n) = V_OL
Ground
f_HSCLK
E, _fHSDR
F
f_HSDRDPA
Differential Waveform
V_OD
p−n=0V
V_OD
Left/Right PLL input clock frequency.
High-speed I/O block: Maximum/minimum LVDS data transfer rate
(f_HSDR = 1/TUI), non-DPA.
High-speed I/O block: Maximum/minimum LVDS data transfer rate
(f_HSDRDPA = 1/TUI), DPA.
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
July 2012 Altera Corporation