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EP2AGX260FF35I3N Datasheet, PDF (29/78 Pages) Altera Corporation – Device Datasheet for Arria II Devices
Chapter 1: Device Datasheet for Arria II Devices
Switching Characteristics
1–29
Table 1–35. Transceiver Specifications for Arria II GZ Devices (Part 2 of 5)
Symbol/
Description
Conditions
–C3 and –I3 (1)
Min Typ
Max
–C4 and –I4
Min Typ
Max
Transceiver Clocks
Calibration block clock
frequency (cal_blk_clk)
—
10
—
125
10
—
125
fixedclk clock frequency
PCIe Receiver
Detect
—
125
—
—
125
—
reconfig_clk clock
frequency
Dynamic
2.5/
2.5/
reconfiguration 37.5
—
50
37.5 —
50
clock frequency
(4)
(4)
Delta time between
reconfig_clks (5)
—
—
—
2
—
—
2
Transceiver block minimum
power-down
(gxb_powerdown) pulse
—
width
1
—
—
1
—
—
Receiver
Supported I/O Standards
1.4-V PCML, 1.5-V PCML, 2.5-V PCML, LVPECL, and LVDS
Data rate
—
600
—
6375
600
—
3750
Absolute VMAX for a receiver
pin (6)
—
—
—
1.6
—
—
1.6
Operational VMAX for a
receiver pin
—
—
—
1.5
—
—
1.5
Absolute VMIN for a receiver
pin
—
-0.4
—
—
-0.4 —
—
Maximum peak-to-peak
differential input voltage VID
(diff p-p) before device
—
configuration
—
—
1.6
—
—
1.6
Maximum peak-to-peak
differential input voltage VID
VICM = 0.82 V
setting
—
—
2.7
—
—
2.7
(diff p-p) after device
configuration
VICM =1.1 V setting
(7)
—
—
1.6
—
—
1.6
Data Rate =
600 Mbps to
5 Gbps
100
—
—
165
—
—
Minimum differential eye
Equalization = 0
opening at receiver serial
input pins (8)
DC gain = 0 dB
Data Rate > 5 Gbps
Equalization = 0 165
—
—
165
—
—
DC gain = 0 dB
VICM = 0.82 V
setting
820 ± 10%
820 ± 10%
VICM
VICM = 1.1 V setting
(7)
1100 ± 10%
1100 ± 10%
Unit
MHz
MHz
MHz
ms
µs
Mbps
V
V
V
V
V
V
mV
mV
mV
mV
July 2012 Altera Corporation
Arria II Device Handbook Volume 3: Device Datasheet and Addendum