EP2AGX260FF35I3N Datasheet, PDF (59/78 Pages) Altera Corporation – Device Datasheet for Arria II Devices

Chapter 1: Device Datasheet for Arria II Devices
Switching Characteristics
1–59
Table 1–49 lists the embedded memory block specifications for Arria II GZ devices.
Table 1–49. Embedded Memory Block Performance Specifications for Arria II GZ Devices (Note 1)
Resources Used
Performance
Memory
Mode
ALUTs
TriMatrix
Memory
C3
I3
C4
Unit
I4
Single port 64 × 10
0
1
500
500
450
450 MHz
MLAB
(2)
Simple dual-port 32 × 20
Simple dual-port 64 × 10
ROM 64 × 10
0
1
500
500
450
450 MHz
0
1
500
500
450
450 MHz
0
1
500
500
450
450 MHz
ROM 32 × 20
0
1
500
500
450
450 MHz
Single-port 256 × 36
0
1
540
540
475
475 MHz
Simple dual-port 256 × 36
0
1
490
490
420
420 MHz
Simple dual-port 256 × 36, with the
read-during-write option set to Old
0
Data
1
340
340
300
300 MHz
True dual port 512 × 18
0
M9K
Block (2)
True dual-port 512 × 18, with the
read-during-write option set to Old
0
Data
1
430
430
370
370 MHz
1
335
335
290
290 MHz
ROM 1 Port
0
1
540
540
475
475 MHz
ROM 2 Port
0
1
540
540
475
475 MHz
Min Pulse Width (clock high time)
—
—
800
800
850
850
ps
Min Pulse Width (clock low time)
—
—
625
625
690
690
ps
Single-port 2K × 72
0
1
440
400
380
350 MHz
Simple dual-port 2K × 72
0
1
435
375
385
325 MHz
Simple dual-port 2K × 72, with the
read-during-write option set to Old
0
Data
1
240
225
205
200 MHz
Simple dual-port 2K × 64 (with ECC) 0
1
300
295
255
250 MHz
M144K ^{True dual-port 4K × 36}
0
Block (2) _{True dual-port 4K × 36, with the}
read-during-write option set to Old
0
Data
1
375
350
330
310 MHz
1
230
225
205
200 MHz
ROM 1 Port
0
1
500
450
435
420 MHz
ROM 2 Port
0
1
465
425
400
400 MHz
Min Pulse Width (clock high time)
—
—
755
860
860
950
ps
Min Pulse Width (clock low time)
—
—
625
690
690
690
ps
Notes to Table 1–48:
(1) To achieve the maximum memory block performance, use a memory block clock that comes through global clock routing from an on-chip PLL
set to 50% output duty cycle. Use the Quartus II software to report timing for this and other memory block clocking schemes.
(2) When you use the error detection CRC feature, there is no degradation in F_MAX.
July 2012 Altera Corporation
Arria II Device Handbook Volume 3: Device Datasheet and Addendum