EPM9320LI84-20 Datasheet, PDF (34/46 Pages) Altera Corporation – Programmable Logic Device Family

MAX 9000 Programmable Logic Device Family Data Sheet
Table 23. IOC Delays
Symbol
Parameter
Conditions
t _{I ODR}
t _{I ODC}
t_{I OC}
t _{I ORD}
t _{I OCOMB}
t _{I OSU}
t_{I OH}
t _{I OCLR}
t _{I OFD}
t _{I NREG}
t _{I NCOMB}
t_OD1
t_OD2
t_OD3
t_XZ
t_ZX1
t_ZX2
t_ZX3
I/O row output data delay
I/O column output data delay
I/O control delay
(6)
I/O register clock-to-output
delay
I/O combinatorial delay
I/O register setup time before
clock
I/O register hold time after
clock
I/O register clear delay
I/O register feedback delay
I/O input pad and buffer to I/O
register delay
I/O input pad and buffer to row
and column delay
Output buffer and pad delay,
Slow slew rate = off,
V _CCIO = 5.0 V
Output buffer and pad delay,
Slow slew rate = off,
V _CCIO = 3.3 V
Output buffer and pad delay,
Slow slew rate = on,
V _CCIO = 5.0 V or 3.3 V
Output buffer disable delay
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
C1 = 5 pF
Output buffer enable delay,
Slow slew rate = off,
V _CCIO = 5.0 V
Output buffer enable delay,
Slow slew rate = off,
V _CCIO = 3.3 V
Output buffer enable delay,
Slow slew rate = on,
V _CCIO = 3.3 V or 5.0 V
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
Speed Grade
Unit
-10
-15
-20
Min Max Min Max Min Max
0.2
0.2
1.5 ns
0.4
0.2
1.5 ns
0.5
1.0
2.0 ns
0.6
1.0
1.5 ns
0.2
2.0
4.0
1.0
5.0
1.5 ns
ns
1.0
1.0
1.0
ns
1.5
3.0
3.0 ns
0.0
0.0
0.5 ns
3.5
4.5
5.5 ns
1.5
2.0
2.5 ns
1.8
2.5
2.5 ns
2.3
3.5
3.5 ns
8.3
10.0
10.5 ns
2.5
2.5
2.5 ns
2.5
2.5
2.5 ns
3.0
3.5
3.5 ns
9.0
10.0
10.5 ns
34
Altera Corporation