EPM9320LI84-20 Datasheet, PDF (17/46 Pages) Altera Corporation – Programmable Logic Device Family

MAX 9000 Programmable Logic Device Family Data Sheet
Figure 10. MAX 9000 IOC
Peripheral Control
Bus [12..0]
VCC
To Row or
Column FastTrack
Interconnect
OE [7..0]
8
13
From Row or
Column FastTrack
Interconnect
CLK [3..0]
4
ENA [5..0]
6 _VCC
CLR [1..0]
2
VCC
DQ
ENA
CLRN
Slew-Rate
Control
I/O pins can be used as input, output, or bidirectional pins. Each IOC has
an IOC register with a clock enable input. This register can be used either
as an input register for external data that requires fast setup times, or as an
output register for data that requires fast clock-to-output performance.
The IOC register clock enable allows the global clock to be used for fast
clock-to-output performance, while maintaining the flexibility required
for selective clocking.
The clock, clock enable, clear, and output enable controls for the IOCs are
provided by a network of I/O control signals. These signals can be
supplied by either the dedicated input pins or internal logic. The IOC
control-signal paths are designed to minimize the skew across the device.
All control-signal sources are buffered onto high-speed drivers that drive
the signals around the periphery of the device. This “peripheral bus” can
be configured to provide up to eight output enable signals, up to four
clock signals, up to six clock enable signals, and up to two clear signals.
Table 6 on page 18 shows the sources that drive the peripheral bus and
how the IOC control signals share the peripheral bus.
Altera Corporation
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