EPM9320LI84-20 Datasheet, PDF (32/46 Pages) Altera Corporation – Programmable Logic Device Family

MAX 9000 Programmable Logic Device Family Data Sheet
Tables 21 through 24 show timing for MAX 9000 devices.
Table 21. MAX 9000 External Timing Characteristics Note (1)
Symbol
Parameter
Conditions
Speed Grade
Unit
-10
-15
-20
Min Max Min Max Min Max
t_PD1
t_PD2
t_FSU
t _FH
t _FCO
t _CNT
f_CNT
Row I/O pin input to row I/O C1 = 35 pF (2)
pin output
Column I/O pin input to
column I/O pin output
C1 = 35 pF EPM9320A
(2)
EPM9320
EPM9400
EPM9480
EPM9560A
EPM9560
Global clock setup time for I/O
3.0
cell
Global clock hold time for I/O
0.0
cell
Global clock to I/O cell output C1 = 35 pF
delay
1.0 (3)
Minimum internal global clock (4)
period
Maximum internal global clock (4)
frequency
144.9
10.0
10.8
11.4
4.8
6.9
15.0
16.0
16.2
16.4
16.6
5.0
6.0
0.0
0.0
1.0 (3) 7.0 1.0 (3)
8.5
117.6
100.0
20.0
23.0
23.2
23.4
23.6
8.5
10.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
32
Altera Corporation