EPM9320LI84-20 Datasheet, PDF (3/46 Pages) Altera Corporation – Programmable Logic Device Family

General
Description
MAX 9000 Programmable Logic Device Family Data Sheet
The MAX 9000 family of in-system-programmable, high-density, high-
performance EPLDs is based on Altera’s third-generation MAX
architecture. Fabricated on an advanced CMOS technology, the EEPROM-
based MAX 9000 family provides 6,000 to 12,000 usable gates, pin-to-pin
delays as fast as 10 ns, and counter speeds of up to 144 MHz. The -10 speed
grade of the MAX 9000 family is compliant with the PCI Local Bus
Specification, Revision 2.2. Table 3 shows the speed grades available for
MAX 9000 devices.
Table 3. MAX 9000 Speed Grade Availability
Device
EPM9320
EPM9320A
EPM9400
EPM9480
EPM9560
EPM9560A
Speed Grade
-10
-15
-20
v
v
v
v
v
v
v
v
v
v
Table 4 shows the performance of MAX 9000 devices for typical functions.
Table 4. MAX 9000 Performance Note (1)
Application
Macrocells Used
Speed Grade
Units
-10
-15
-20
16-bit loadable counter
16-bit up/down counter
16-bit prescaled counter
16-bit address decode
16-to-1 multiplexer
16
144
118
100
MHz
16
144
118
100
MHz
16
144
118
100
MHz
1
5.6 (10)
7.9 (15)
10 (20)
ns
1
7.7 (12.1)
10.9 (18)
16 (26)
ns
Note:
(1) Internal logic array block (LAB) performance is shown. Numbers in parentheses show external delays from row
input pin to row I/O pin.
The MAX 9000 architecture supports high-density integration of system-
level logic functions. It easily integrates multiple programmable logic
devices ranging from PALs, GALs, and 22V10s to field-programmable
gate array (FPGA) devices and EPLDs.
Altera Corporation
3