AK4125_07 Datasheet, PDF (9/26 Pages) Asahi Kasei Microsystems – 192kHz / 24Bit High Performance Asynchronous SRC

SWITCHING CHARACTERISTICS
(Ta=25°C; AVDD, DVDD=3.0 ∼ 3.6V; C_L=20pF)
Parameter
Symbol
min
typ
Master Clock Timing
Frequency
fCLK
1.024
Pulse Width Low
tCLKL 0.4/fCLK
Pulse Width High
tCLKH 0.4/fCLK
LRCK for Input data (ILRCK)
Frequency
Duty Cycle
Slave Mode
Master Mode
fs
8
Duty
48
50
Duty
50
LRCK for Output data (OLRCK)
Frequency
Duty Cycle
Slave Mode
Master Mode
fs
8
Duty
48
50
Duty
50
Audio Interface Timing
Input PORT (Slave mode)
IBICK Period (8kHz ∼ 108kHz)
(108kHz ∼ 216kHz)
tBCK
tBCK
1/128fs
1/64fs
IBICK Pulse Width Low
tBCKL
27
Pulse Width High
tBCKH
27
ILRCK Edge to IBICK “↑”
(Note 7) tLRB
15
IBICK “↑” to ILRCK Edge
(Note 7) tBLR
15
SDTI Hold Time from IBICK “↑”
tSDH
15
SDTI Setup Time to IBICK “↑”
tSDS
15
Input PORT (Master mode)
IBICK Frequency
fBCK
64fs
IBICK Duty
IBICK “↓” to ILRCK
SDTI Hold Time from IBICK “↑”
SDTI Setup Time to IBICK “↑”
dBCK
50
tMBLR
−20
tSDH
15
tSDS
15
Output PORT (Slave mode)
OBICK Period (8kHz ∼ 108kHz)
(108kHz ∼ 216kHz)
tBCK
tBCK
1/128fs
1/64fs
OBICK Pulse Width Low
tBCKL
27
Pulse Width High
tBCKH
27
OLRCK Edge to OBICK “↑”
(Note 7) tLRB
20
OBICK “↑” to OLRCK Edge
(Note 7) tBLR
20
OLRCK to SDTO (MSB) (Except I²S mode) tLRS
OBICK “↓” to SDTO
tBSD
Output PORT (Master mode)
OBICK Frequency
fBCK
64fs
OBICK Duty
OBICK “↓” to OLRCK
OBICK “↓” to SDTO
dBCK
50
tMBLR
−20
tBSD
−20
Reset Timing
PDN Pulse Width
(Note 8) tPD
150
Note 7. BICK rising edge must not occur at the same time as LRCK edge.
Note 8. The AK4125 can be reset by bringing the PDN pin = “L”.
[AK4125]
max
41.472
216
52
216
52
Units
MHz
ns
ns
kHz
%
%
kHz
%
%
ns
ns
ns
ns
ns
ns
ns
ns
Hz
%
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
20
ns
20
ns
Hz
%
20
ns
20
ns
ns
MS0379-E-04
-9-
2007/07