AK4125_07 Datasheet, PDF (22/26 Pages) Asahi Kasei Microsystems – 192kHz / 24Bit High Performance Asynchronous SRC

[AK4125]
2. Jitter Tolerance
Figure 17 shows the jitter tolerance to ILRCK and IBICK. The jitter quantity is defined by the jitter frequency and the jitter
amplitude shown in Figure 17. When the jitter amplitude is 0.01Uipp or less, the AK4125 operates normally regardless of
the jitter frequency.
10.00
AK4125 Jitter Tolerance
1.00
0.10
(2)
0.01
0.00
1
10
(3)
(1)
100
Jitter Frequency [Hz]
1000
10000
(1) Normal operation
(2) There is a possibility that the distortion degrades. (It may degrade up to about −50dB.)
(3) There is a possibility that the output data is lost.
Note:
- When PLL2-0 = “L/L/L”, “L/L/H”, “L/H/L”, the jitter amplitude is for ILRCK and 1UI (Unit Interval) is one
cycle of ILRCK. When FSI = 48kHz, 1UI is 1/48kHz = 20.8μs.
- When PLL2-0 = “H/*/*” (*: Don’t care), the jitter amplitude is for IBICK and 1UI (Unit Interval) is one cycle of
IBICK. When FSI = 48kHz, 1UI is 1/(64 x 48kHz) = 326ns.
Figure 17. Jitter Tolerance
Tracking to the Input Sampling Frequency
When the ILRCK is generated by an external PLL, it may take time to settle after changing the input sampling frequency
because the response of an external PLL to the frequency change is slow. The AK4125 operates normally up to 23%/sec
speed but outputs incorrect data at the speed of the frequency change over 23%/sec.
MS0379-E-04
- 22 -
2007/07