AK4125_07 Datasheet, PDF (12/26 Pages) Asahi Kasei Microsystems – 192kHz / 24Bit High Performance Asynchronous SRC

[AK4125]
OPERATION OVERVIEW
■ System Clock & Audio Interface Format for Input PORT
The input port works in master mode or slave mode. An internal system clock is created by the internal PLL using ILRCK
(Mode 0 ∼ 2 of Table 2) or IBICK (Mode 4 ∼ 7 of Table 2) in slave mode. The MCLK is not needed in slave mode. And
an internal system clock is created by IMCLK (Mode 8 ∼ 15 of Table 2) in master mode. The PLL2-0 pins and IDIF2-0
pins select the master/slave and PLL mode. The PLL2-0 pins and IDIF2-0 pins should be controlled when the PDN pin =
“L”.
The IDIF2-0 pins select the audio interface format for the input port. The audio data is MSB first, 2’s compliment format.
The SDTI is latched on the rising edge of IBICK. Select the audio interface format when the PDN pin = “L”. When in
BYPASS mode, both IBICK and OBICK are fixed to 64fs.
Mode
0
1
2
3
4
5
6
7
IDIF2
L
L
L
L
H
H
H
H
IDIF1
L
L
H
H
L
L
H
H
IDIF0
SDTI Format
ILRCK IBICK IBICK Freq
L
16bit, LSB justified
≥ 32fsi
H
20bit, LSB justified
≥ 40fsi
L 24/20bit, MSB justified Input Input
≥ 48fsi
H 24/16bit, I²S Compatible
≥ 48fsi or 32fsi
L
24bit, LSB justified
≥ 48fsi
H
L
24bit, MSB justified
24bit, I²S Compatible
Output Output
64fs
64fs
H
Reserved
Table 1. Input Audio Interface Format (Input PORT)
Master / Slave
Slave
Master
Mode Master / Slave
0
1
2
Slave
IMCLK = DVSS
3
IBICK = Input
4
ILRCK = Input
5
6
7
8
9
10
Master
11 IMCLK = Input
12 ^{IBICK = Output}
13 ^{ILRCK = Output}
14
15
PLL2
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
PLL1 PLL0 ILRCK Freq IBICK Freq IMCLK
L
L
L
H
8k ∼ 96kHz
8k ∼ 216kHz
Depending on
IDIF2-0
Not
needed.
H
L
16k ∼ 216kHz
(Note 9)
(Note 10)
(Note 12)
H
H
Reserved
L
L
H
L
H
L
8k ∼ 216kHz
(Note 10)
32fsi (Note 11)
64fsi
128fsi
Not
needed.
(Note 12)
H
H
64fsi
L
L
8k ∼ 216kHz
128fs
L
H
8k ∼ 108kHz
256fs
H
L
8k ∼ 54kHz
512fs
H
H
8k ∼ 216kHz
64fs
L
L
8k ∼ 216kHz
128fs
192fs
L
H
8k ∼ 108kHz
384fs
H
L
8k ∼ 54kHz
768fs
H
H
8k ∼ 216kHz
192fs
Table 2. PLL Setting (Input PORT)
SMUTE
(Note 13)
Manual
Semi-Auto
Manual
Semi-Auto
Manual
Semi-Auto
Manual
Semi-Auto
Note 9. PLL lock rage is changed by the value of R and C connected FILT pin. Refer to “PLL Loop Filter”.
Note 10. IBCIK must be continuous except when the clocks are changed.
Note 11. IBCIK = 32fsi is supported only 16bit LSB justified and I²S Compatible.
Note 12. Fixed to DVSS.
Note 13. Refer to “Soft Mute Operation” for Manual mode and Semi-Auto mode.
MS0379-E-04
- 12 -
2007/07