AK4125_07 Datasheet, PDF (18/26 Pages) Asahi Kasei Microsystems – 192kHz / 24Bit High Performance Asynchronous SRC

[AK4125]
■ Internal Reset Function for Clock Change
The AK4125 is reset automatically when the output clock is stopped. If the output clock is started again, normal data is
output within 100ms.
■ Sequence of Changing Clocks
The change of the clock supplied to AK4125 is shown in Figure 13.
External clocks
(Input port
or Output port)
Clocks 1
Don’t care
Clocks 2
PDN pin
< 100ms
(Internal state)
Normal operation Power-down
PLL lock &
fs detection
Normal operation
SDTO
Normal data
Note1
Normal data
SMUTE (Note2,
recommended)
0dB
Att.Level
-∞dB
1024/fso
1024/fso
Figure 13. Sequence of changing clocks
Note 1. The data on SDTO may cause a clicking noise. To prevent this, set “0” to the SDTI from GD before the PDN
pin changes to “L”. It makes the data on SDTO remain as “0”.
Note 2. SMUTE can also remove the unknown data.
■ UNLOCK pin
The UNLOCK pin outputs “L” when the internal PLL is locked. When the internal PLL is unlocked, the UNLOCK pin
outputs “H” and the SDTO = “0”. When the PDN pin = “L”, the UNLOCK pin outputs “H”.
MS0379-E-04
- 18 -
2007/07