AK4125_07 Datasheet, PDF (19/26 Pages) Asahi Kasei Microsystems – 192kHz / 24Bit High Performance Asynchronous SRC

[AK4125]
■ PLL Loop Filter
The C1 and R should be connected in series and attached between FILT pin and AVSS in parallel with C2. (Figure 14,
Table 6, Table 7) Please be careful the noise onto the FILT pin. When using IBICK, the value of external element is not
dependent on the IBICK input frequency.
AK4125
FILT
R
C2
C1
AVSS
Figure 14. PLL Loop Filter
[Input PORT in slave mode]
1. When using ILRCK
PLL2
L
L
L
PLL1
L
L
H
PLL0
ILRCK
R [Ω]
C1 [μF]
L
8k ∼ 96kHz
1.8k ± 5%
0.68 ± 30%
H
8k ∼ 216kHz
16k ∼ 216kHz
1k ± 5%
1.5k ± 5%
1.0 ± 30%
0.68 ± 30%
L
8k ∼ 216kHz
16k ∼ 216kHz
1k ± 5%
1.5k ± 5%
1.0 ± 30%
0.68 ± 30%
Table 6. PLL Loop Filter (ILRCK Mode)
C2 [nF]
0.68 ± 30%
2.2 ± 30%
0.68 ± 30%
2.2 ± 30%
0.68 ± 30%
- Note. Smaller value can be selected for the capacitors (C1, C2) in case of ILRCK range from 16kHz to 216kHz..
2. When using IBICK
PLL2
H
PLL1
*
PLL0
ILRCK
R [Ω]
C1 [μF]
*
8k ∼ 216kHz 470 ± 5%
0.22 ± 30%
Table 7. PLL Loop Filter (IBICK Mode, *: Don’t care)
C2 [nF]
1.0 ± 30%
Note. The IBCIK must be continuous except when the clocks are changed.
Note. IBCIK = 32fsi is supported only 16bit LSB justified and I²S Compatible.
[Input PORT in master mode]
1. When IMCLK is 256fs, 384fs, 512fs or 768fs, any external parts shown in Figure 14 are not required.
2. When IMCLK is 128fs or 192fs, the external parts shown in Table 7 are required.
MS0379-E-04
- 19 -
2007/07