AK4125_07 Datasheet, PDF (20/26 Pages) Asahi Kasei Microsystems – 192kHz / 24Bit High Performance Asynchronous SRC

[AK4125]
SYSTEM DESIGN
Figure 15, Figure 16 show the system connection diagram. The evaluation board demonstrates application circuits, the
optimum layout, power supply arrangements and measurement results.
• Input PORT: Slave Mode, IBICK lock mode (64fsi), 24bit MSB justified
• Output PORT: Slave mode, 24bit MSB justified
• Dither = OFF
0.22μ
470 _1.0n
1 FILT
2 AVSS
10μ
AVDD 30 _0.1μ
DVSS 29
Reset
fsi
64fsi
3 PDN
4 SMUTE
5 DITHER
6 PLL2
7 ILRCK
AK4125
DVDD 28
0.1μ
OMCLK 27
OLRCK 26
OBICK 25
fso
64fso
SDTO 24
8 IBICK
ODIF1 23
DSP, uP
9 SDTI
10 IDIF0
ODIF0 22
CMODE2 21
11 IDIF1
CMODE1 20
12 IDIF2
CMODE0 19
13 PLL0
IMCLK 18
14 PLL1
OBIT1 17
15 UNLOCK
OBIT0 16
Supply
3.0 ~ 3.6V
DSP
Note:
- AVSS and DVSS of the AK4125 should be distributed separately from the ground of external digital
devices (MPU, DSP etc.).
- All digital input pins should not be left floating.
Figure 15. Typical Connection Diagram (Slave mode)
MS0379-E-04
- 20 -
2007/07